ST STM32F4 Series User Manual

The STM32 Cortex-M4 instruction set PM0214
150/262 PM0214 Rev 9
VMSR
Move to floating-point System Register from Arm
Core register
VMSR on page 170
VMUL Multiply floating-point VMUL on page 171
VNEG Floating-point negate VNEG on page 172
VNMLA Floating-point multiply and add
VNMLA, VNMLS, VNMUL on
page 173
VNMLS Floating-point multiply and subtract
VNMLA, VNMLS, VNMUL on
page 173
VNMUL Floating-point multiply
VNMLA, VNMLS, VNMUL on
page 173
VPOP Pop extension registers VPOP on page 174
VPUSH Push extension registers VPUSH on page 175
VSQRT Floating-point square root VSQRT on page 176
VSTM Store Multiple extension registers VSTM on page 177
VSTR Stores an extension register to memory VSTR on page 178
VSUB Floating-point Subtract VSUB on page 179
Table 35. Floating-point instructions
Mnemonic Brief description See

ST STM32F4 Series Specifications

General

Series	STM32F4
Core	ARM Cortex-M4
Clock Speed	Up to 180 MHz
Flash Memory	Up to 2 MB
RAM	Up to 384 KB
Operating Voltage	1.8 V to 3.6 V
DAC	12-bit, up to 2 channels
Timers	Up to 17 timers
Communication Interfaces	USB, CAN, SPI, I2C, USART, Ethernet
Operating Temperature	-40°C to 85°C
Package	LQFP, WLCSP, BGA

Summary

Introduction to the STM32 Cortex-M4 Programming Manual

Cortex-M4 Processor Features and Benefits

Summarizes key advantages: outstanding performance, enhanced debug, efficient core, low power, and security.

Reference Documents for STM32 Cortex-M4

Lists datasheets and reference manuals available from STMicroelectronics website for further details.

About this document

Typographical Conventions Used

Explains conventions for highlighting important notes, cross-references, and code elements.

Abbreviations for Registers

Lists common abbreviations used in register descriptions, such as (rw), (r), and (w).

STM32 Cortex-M4 Processor and Core Peripherals Overview

Introduces the Cortex-M4 processor, its architecture, and integrated core peripherals.

The Cortex-M4 Processor

Cortex-M4 Programmers Model

Describes processor modes, privilege levels, execution states, and stack usage.

Cortex-M4 Memory Model

Explains the memory map, access behavior, and bit-banding features.

Cortex-M4 Exception Model

Covers exception states, types, handlers, priorities, and grouping mechanisms.

The STM32 Cortex-M4 Instruction Set

Instruction Set Summary and Syntax

Lists supported instructions, syntax conventions, and flexible operand usage.

Memory Access Instructions

Details instructions for loading and storing data from memory.

General Data Processing Instructions

Covers arithmetic, logical, shift, and data manipulation instructions.

Multiply and Divide Instructions

Explains signed/unsigned multiply, accumulate, divide, and saturation instructions.

Saturating Instructions

Describes instructions performing saturation arithmetic on signed/unsigned values.

Core Peripherals

Nested Vectored Interrupt Controller (NVIC)

Details the NVIC's interrupt handling, priority levels, and registers.

System Control Block (SCB) Registers

Explains SCB registers for system control, configuration, and exception reporting.

SysTick Timer (STK) Functionality

Describes the SysTick timer for system timing and RTOS tick generation.

Document Revision History