Chapter 2: Installation
2-15
LED4
A-SATA1
A-SATA0
I-SATA1
I-SATA0
I-SATA3
I-SATA2
JPUSB2
1
JPUSB1
1
JLED1
1
1
JPL1
1
JPME2
1
JPL2
1
JPAC1
1
1
JWD1
1
JVR1
1
JBT1
JSTBY1
1
JSD1
COM1
JF1
DESIGNED IN USA
C7Z97-OCE
REV:1.01
BIOS
LICENSE
FOR HOME OR OFFICE USE
With FCC Standards
Tested to Comply
JPW2
1
1
JL1
1
JL2
JWOR1
JSPDIF_OUT
1
JI2C1
1
JI2C2
1
JPW1
MAC CODE
BAR CODE
1
JITP1
2
LED1
SP1
JCHLED1
1
FAN3
1
FAN2
FAN5
1
FAN1
FAN4
1
1
JD1
JAUDIO1
POWER
BUTTON
(3.0)
A-SATA0A-SATA1
I-SATA4I-SATA5
I-SATA2I-SATA3
I-SATA0I-SATA1
CLEAR CMOS
1-2
ENABLE
JPUSB2:USB6/7 Wake Up
2-3
DISABLE
ENABLE
DISABLE
JPUSB1:USB0/1 Wake Up
2-3
1-2
(3.0)
USB 2/3
USB 12/13
USB 14/15(3.0)
CPU
CPU_SLOT2 PCI-E 3.0 X4 (IN X16)
PCH_SLOT1 PCI-E 2.0 X1 (INX4)
PCH_SLOT5 PCI-E 2.0 X1 (INX4)
PCH_SLOT3 PCI-E 2.0 X1 (INX4)
LAN2
LAN1
JWD1:
JBR1:
2-3:BIOS RECOVERY
1-2:NORMAL
JPME1:
2-3:ME RECOVERY
1-2:NORMAL
JSD1:
ENABLE
LAN2
DISABLE
2-3
1-2
JPL2
LAN1
DISABLE
ENABLE
2-3
1-2
JPL1
JWOR1:
2-3:NMI
1-2:RST
WATCH DOG
CPU
2-3:ME MANUFACTURING MODE
USB 0/1
1-2:NORMAL
JPME2:
SATA DOM PWR
JL1:
JLED1:
3 PIN POWER LED
AUDIO FP
HDD PWR
LEDLED
DIMMB1
DIMMB2
NIC1
SPEAKER:1-4
JD1:
BUZZER:3-4
JI2C1/JI2C2
ON:ENABLE
OFF:DISABLE
NIC2
HD AUDIO
WAKE ON RING
USB4/5
USB6/7
OH/FF
LED
X
CHASSIS INTRUSION
DIMMA1
DIMMA2
RST
PWR
JF1
ON
ALWAYS POPULATE BLUE SOCKET FIRST
UNB NON-ECC DDR3 DIMM REQUIRED
CPU_SLOT4 PCI-E 3.0 X8 (IN X16)
CPU_SLOT6 PCI-E 3.0 X16
VGA/DVI
2-3:DISABLE
1-2:ENABLE
JPAC1:AUDIO
JPME1
OC1
OC2
OC3
HOME
HDMI/DP
1
MEMORY OC
JVR2
PS2
OC FRONT PANEL
JBR1
M
JBT1
BIOS RESTORE
USB6_charger
CLEAR CMOS
PCI-E M.2
CONNECTOR
A. Backpanel USB 2.0 #0
B. Backpanel USB 2.0 #1
C. Backpanel USB 3.0 #2
D. Backpanel USB 3.0 #3
E. Backpanel USB 3.0 #12
F. Backpanel USB 3.0 #13
G. USB 2.0 Header #4/5
H. USB 2.0 Header #6/7
I. USB 3.0 Header #14/15
Universal Serial Bus (USB)
Two Universal Serial Bus 2.0 ports (0/1) and four USB 3.0 ports
(2/3,12/13) are located on the I/O back panel. In addition, two USB
2.0 headers (four ports: 4/5, 6/7), and one USB 3.0 header (two ports:
14/15) are also located on the motherboard to provide front chassis
access using USB cables (not included). See the tables below for pin
denitions.
Back Panel USB (2.0) #0/1, USB (3.0) #2/3,
12/13 Pin Denitions
Pin# Denition Pin# Denition
1 +5V 5 +5V
2 USB_PN1 6 USB_PN0
3 USB_PP1 7 USB_PP0
4 Ground 8 Ground
Front Panel USB (2.0) Header #4/5, 6/7
Pin Denitions
Pin # Denition Pin # Denition
1 +5V 2 +5V
3 USB_PN2 4 USB_PN3
5 USB_PP2 6 USB_PP3
7 Ground 8 Ground
9 Key 10 Ground
A
Front Panel USB (3.0) Header #14/15
Pin Denitions
Pin# Pin# Signal Name Description
1 10 VBUS Power
2 11 D- USB 2.0 Differential Pair
3 12 D+
4 13 Ground Ground of PWR Return
5 14 StdA_SSRX- SuperSpeed Receiver
6 15 StdA_SSRX+ Differential Pair
7 16 GND_DRAIN Ground for Signal Return
8 17 StdA_SSTX- SuperSpeed Transmitter
9 18 StdA_SSTX+ Differential Pair
C
E
B