VIPA CPU Series - Page 33

Manual VIPA System 200V Chapter 2 Hardware description
HB97E - CPU - RE_21x-1Bx06 - Rev. 13/20 2-7
Order no. 214-1BC06
Time
Real-time clock buffered
9
Clock buffered period (min.) 30 d
Accuracy (max. deviation per day) 10 s
Number of operating hours counter 8
Clock synchronization -
Synchronization via MPI -
Synchronization via Ethernet (NTP) -
Address areas (I/O)
Input I/O address area 1024 Byte
Output I/O address area 1024 Byte
Input process image maximal 128 Byte
Output process image maximal 128 Byte
Digital inputs 8192
Digital outputs 8192
Digital inputs central 512
Digital outputs central 512
Integrated digital inputs -
Integrated digital outputs -
Analog inputs 512
Analog outputs 512
Analog inputs, central 128
Analog outputs, central 128
Integrated analog inputs -
Integrated analog outputs -
Communication functions
PG/OP channel
9
Global data communication
9
Number of GD circuits, max. 4
Size of GD packets, max. 22 Byte
S7 basic communication
9
S7 basic communication, user data per job 76 Byte
S7 communication
9
S7 communication as server
9
S7 communication as client -
S7 communication, user data per job 160 Byte
Number of connections, max. 16
Functionality Sub-D interfaces
Type MP²I
Type of interface RS485
Connector Sub-D, 9-pin, female
Electrically isolated -
MPI
9
MP²I (MPI/RS232)
9
DP master -
DP slave -
Point-to-point interface -
Functionality MPI
Number of connections, max. 16
PG/OP channel
9
Routing -
Global data communication
9
S7 basic communication
9
S7 communication
9
S7 communication as server
9
S7 communication as client -