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VIPA CPU Series User Manual

VIPA CPU Series
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Manual VIPA System 200V Chapter 3 Deployment CPU 21x-1Bx06
HB97E - CPU - RE_21x-1Bx06 - Rev. 13/20 3-19
The CPUs include security mechanisms like a watchdog (100ms) and a
parameterizable cycle time surveillance (parameterizable min. 1ms) that
stop res. execute a RESET at the CPU in case of an error and set it into a
defined STOP state.
The VIPA CPUs are developed function secure and have the following
system properties:
Event concerns Effect
RUN STOP
general
BASP (Befehls-Ausgabe-Sperre, i.e. command
output lock) is set.
central digital outputs The outputs are disabled.
central analog outputs The Outputs are disabled.
- Voltage outputs issue 0V
- Current outputs 0...20mA issue 0mA
- Current outputs 4...20mA issue 4mA
If configured also substitute values may be
issued.
decentral outputs Same behavior as the central digital/analog
outputs.
decentral inputs The inputs are cyclically be read by the decentra-
lized station and the recent values are put at
disposal.
STOP RUN
res. PowerON
general First the PII is deleted, then OB 100 is called. After
the execution of the OB, the BASP is reset and the
cycle starts with:
Delete PIO Read PII OB 1.
central analog outputs The behavior of the outputs at restart can be
preset.
decentral inputs The inputs are cyclically be read by the decentra-
lized station and the recent values are put at
disposal.
RUN general The program execution happens cyclically and can
therefore be foreseen:
Read PII OB 1 Write PIO.
PII = Process image inputs
PIO = Process image outputs
Function securit
y

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VIPA CPU Series Specifications

General IconGeneral
SeriesVIPA CPU Series
Communication PortsEthernet
Power Supply24 V DC
Operating Temperature0°C to +60°C
CertificationsCE, UL, cUL

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