Xerox 550 User Manual

of lPSD is a 1, or is disarmed if bit 11 of lPSD is a O.
If bit 10 of lPSD is a 0, no interrupt level is affected
in any way, regardless of whether bit 11 of lPSD is 1
or O. If bit 10 of the lPSD is a 0 and bit 11 of lPSD
is 1, the PDF flag is cleared. (Interrupt levels are de-
scribed in detai I in Chapter 2, "Interrupt System". )
Bit position
10 {Cl} 11 {AD} Function
o Clear and disarm interrupt level.
Clear and arm interrupt level.
o
Clear PDF flag.
o
o
No control action.
3. The PDF flag is normally reset by the last instruction
of a trap routine, which is an lPSD instruction having
bit 10 equal to 0 and bit 11 equal to 1.
These portions of
the effective doubleword that correspond
to undefined fields in the program status words are ignored.
Affected: (PSWs), interrupt system if (I) 10 = 1
ED
O
_
3
- CC; ED
5
_
7
-
FS,FX,FN;
ED -MS· ED - MM·
8 ' 9 '
EDll - AM;
ED
15
_
31
- IA; ED
32
_
35
- WK;
ED
37
_
39
- CI, II, EI; if (1)8 = 1, ED
56
_
59
- RP
If (1) 10 = 1 and (1) 11 = 1, clear and arm interrupt
If (1)10 = 1 and (I}ll = 0, clear and disarm interrupt
XPSD EXCHANGE PROGRAM STATUS WORDS
{Doubleword index alignment, privileged}
EXCHANGE PROGRAM
STATUS WORDS stores the cur-
rently active PSWs in the doubleword location addressed by
the effective address of the XPSD instruction. The follow-
ing doubleword is then accessed from memory and loaded
into the active PSWs registers.
94
Control Instructi ons
The
XPSD instruction is used for three distinct types of
operations: as a norma I instruction in an ongoing program;
as an interrupt instruction; and as a trap instruction.
Control bits used in the XPSD instructions are:
Bit
Position
8
Designation
lP
Control
Function
load pointer
control
Where used
All XPSDs
9
AI Address Increment Trap XPSD
10
AT
Addressing type All XPSDs
The
effective address of an XPSD instruction is generated
in one of the following ways:
XPSD (normal instruction)
When an XPSD instruction is encountered in the course of
execution of norma I programs, the AT· (bit 10) of the in-
struction determines the type of addressing to be used.
If AT = 0, the reference address is 20 bits (12-31). Index-
ing is not allowed. Indirect addressing is allowed with the
same constraints as the reference address. Addressing is
always real, independent of the current PSWs.
If AT = 1, the reference address is 17 bits (15-31). Address
calculations are according to standard addressing rules as
determined by the current PSWs. Indexing and indirect ad-
dressing are allowed.
XPSD (interrupt instruction)
An XPSD instruction (in an interrupt location) executed as
a result of an interrupt is called an interrupt instruction.
The type of addressing to be used is determined by the basic
processor mode and the AT (bit 1O) of the instruction.
In the extended addressing mode (MA = 1 and MM = 0), the
AT bit is used to determine the type of addressing to be
used. If AT = 0, the referen ce address is 20 bits (12-31).
Indexing is not allowed. Indirectaddressing is allowed with
the same constraints as the reference address. Addressing is
always real, independent of the current PSWs. If AT = 1,
the reference address is 17 bits (15-31). Address calcula-
tions are according to standard addressing rules as deter-
mined by the current PSWs. Indexing and indirect addressing
are allowed.
When the addressing mode is not extended addressing, the
reference address is 20 bits (12-31). If AT = 0, indexing
is not allowed. Indirect addressing is allowed with the
same constraints as the reference address. Addressing is
always real, independent of the current PSWs. If AT = 1,
the 20-bit reference address is subject to PSWs bit 9,
as is the contents of the indirect address if indirect is
specified.

Xerox 550 Specifications

General

Monthly Duty Cycle	Up to 300, 000 pages
Connectivity	Ethernet, USB
Print Speed (Color)	Up to 50 ppm
Duplex Printing	Standard
Printer Type	Laser
Supported Operating Systems	Windows, macOS, Linux
Paper Size	A4, Legal, Letter