Otherwise,
the
first word
of
the
next
10CD
is fetched and
loaded as described
above,
and
the
second word is fetched
and loaded as described below.
Since the Transfer in Channel command permits 10CDs to
be
fetched
from nonconsecutive locations, 10CDs
contain-
ing Transfer in Channel commands may be included within
a command list
either
to
achieve
command list continuity
from one segment
af
a command list to
another
segment
or
to construct
reiterative
loops.
For
all
10CDs,
except
a control
10CD
containing a Trans-
fer in Channel command, the lOP will
automatically
access
main memory
at
the appropriate time, as determined by
the
priority
that
prevails for accessing main memory, and fetch
the
second word of
the
10CD
from
the
next consecutive
ascending (odd) memory word location of
the
command list
and increment the command address register by one. Thus,
in
all
cases,
after
a fetching operation is completed, the
content
of
the
command address register
wi
II
be an even
(or doubleword) address.
The contents
of
the second word are stored in appropriate
registers within the
I/O
subchannel. Depending upon the
I/O
order, as described under "Execution Phase", the
con-
tents of the various fields
are
either
used or ignored.
In
addition to the
lOP
Control Error (IOPCE), the following
types
of
"unusual end" conditions may be
detected
during
the fetching phase
of
an
I/O
operation: Memory Address
Error (MAE), Control Check Fault (CCF),
lOP
Memory Error
(IOPME),
Bus
Check
Fault (BCF), and Memory Interface
Error (MIE).
The
detection
of
any
of these errors causes
the
I/O
operation
to
be terminated and if
the
IUE
flag is set to
a 1,
an
"unusual end" interrupt is requested.
EXECUTION
PHASE
Although
the
services of the
BP
are
not required during
this phase,
the
BP
may
at
any time
execute
either
a TIO,
TDV,
or POL instruction without interfering with the
I/o
operation.
However, excessive testing may cause a
data
overrun
condition.
The
BP
may also
execute
either
an
HIO or RIO instruction and stop the
I/O
operation.
After
the second word
of
an IOCD is fetched and providing
no
"unusual
end"
condition was
detected,
the
10CD
is
executed
as prescribed by the parameters
contained
therein.
As
a
function
of
the
order and the status
of
the Skip flag, if
applicable,
an
10CD
may be
executed
in one
of
five ways,
as described below:
1.
Certain
Control orders (e.
g.,
Stop) may be
executed
by the
device
while the
lOP
monitors the operation in
accordance
with the
applicable
control flogs. Since
no
memory accesses and
data
(or information) transfers
occur,
the
contents
of
the memory byte address
reg-
ister, write key register, and byte count register may
be ignored.
Other
Control orders (e.
g.,
Rewind for a
magnetic
tape
unit) are listed and described in
applic-
able
Xerox peripheral equipment
reference
manuals.
132
I/O
Operation
Phases
Depending upon the control function performed, certain
Control orders may be a part
of
an
I/O
operation
which may be continued
after
the Control order
is
executed.
For example, an
I/O
operation involving
a magnetic
tape
unit may contain a Rewind order to
reposition the tape prior to reading (or writing) one or
more records.
Note:
Within the
context
of
the above explanation,
the Control order is defined to be one
that
does not transfer
any
information; thus,
data
chaining is precluded within the 10CD
con-
taining the Control order; however, command
chaining may be specified. Control orders
that
involve information transfers when
executed
are
described below (see paragraphs 2 and 4).
2. If the order specifies an input operation (e.
g.,
Read,
Read Backward,
or
Sense) and the Skip flag is coded
as a 0, all parameters
of
the current 10CD may be
applicable.
As
a result
of
receiving an appropriate
input order, the devi ce transmi ts
data
(Read, or Read
Backward order) or information
from
special registers
(Sense order) into
data
buffers
of
the
associated
I/O
subchannel within the lOP.
Depending upon the priority
that
prevai
Is
for accessing
main memory, the lOP accesses a memory word location
{as
specified by the current memory byte address},
transfers
up
to four bytes
of
data
or i nformati on
from
the
data
buffers
to
a memory unit, provides a write
key, and increments
(or
decrements, if Read Backward
order) the memory byte address and decrements the
byte
count
by one for
each
byte transferred
out
of
the
data
buffers.
The write key
is
evaluated
against
the
preassigned
write lock for the memory word location accessed.
If
the
write key is
valid
for
each
memory word
loca-
tion accessed, the input operation continues, as
des-
cribed
above, unti I
it
is completed or terminated
by an "unusual end" condition;
other
than Write
Lock
Violation. If the write key
is
not
valid,
the memory
unit
(1)
generates and transmits a Write
lock
Viola-
tion (WlV) signal to the
lOP,
(2) rejects the new
data,
and (3) does not disturb
the
previous contents of
the
memory word location accessed.
If
the write key is invalid for any memory word location
accessed and the
HTE
flag
is
coded as a 1, the input
operation is terminated immediately upon
receipt
of
a
WlV
signal (see "Termination Phase
ll
).
If
the
HTE
flag
is
coded as a 0, the memory unit may
accept
or
reiect
the
date
or
infermation,
based
on
the
write
key/write
lock
evaluation
for
each
memory word
location accessed, without
affecting
the operations
within the
lOP,
device
controller,
or
device.
The
input operation continues unti I
either
completed or
terminated
by
an "unusual end" condition, other than
a Write
lock
Violation.
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