If
the
effective
address
of
BDR
is
unavailable
to the program
(slave
or
master-protected
mode) for instruction
access
and
the
branch
condition
is
satisfied,
or
if
the
effective
address
of
BDR
is
nonexistent,
the
basi c processor aborts
execution
of
the
BDR
instruction
and
traps to
location
X'40'.
In
this
case,
the
instruction address stored by the
XPSD
instruction
in
location
X'40'
is
the
virtual
address
of
the
aborted
BDR
instruction.
If
the
basic
processor traps
because
of
instruc-
tion
access
protection,
register R
wi"
contain
the
value
that
existed
just before
the
BDR
instruction.
If
a memory
parity
error
occurs
due
to
the
accessing
of
the
instruction to whi ch
the
program
is
branching,
the
basic processor aborts
execu-
tion
of
the
BDR
and traps to
location
X'4C'
with register R
unchanged.
BAL
BRANCH
AND
LINK
(Word index alignment)
BRANCH
AND
LINK determines
the
effective
virtual
ad-
dress, loads
the
updated instruction address (the
virtual
ad-
dress of
the
next
instruction
in
normal
sequence
after
the
BAL
instruction) into
bit
positions 15-31
of
general
regis-
ter
R,
clears
bit
positions
0-14
of register R
to
O's
and
then
replaces
the
updated
instruction address with
the
effective
virtual
address. Instruction
execution
proceeds with
the
instruction
pointed
to by the
effective
address
of
the
BAL
instruction.
The
BAL
instruction in real
extended
addressing will store
the
full address
of
the
next instruction in
the
specified
R
register.
Positions
0-9
of
the
specified
register
wi"
be
set
equal
to
zero.
Affected:
(R)
I (IA)
IA
- R
15
-
31
; 0 -
RO-l~
EVA
15
_
31
-
IA
If
the
effective
address
of
BAL
is
unavailable
to the program
(slave
or
master-protected
mode) for instruction
access
and
the
branch
condition
is
satisfied,
or if the
effective
address
of
BAL
is
nonexistent,
the
basic
processor aborts
execution
of
the
BA
L instruction
and
traps to
location
X'40'
(nonallowed
operation
trap).
In
this
case,
the
instruction address stored
by
the
XPSD instruction in
location
X'40'
is
the
virtual
ad-
dress
of
the
aborted
BAL
instruction.
If
the
basic
processor
traps
because
of
instruction
access
protection,
register R will
contain
the
updated
instruction address. If a memory
parity
error
occurs
due
to
the
accessing
of
the
instruction to which
the
program is
branching,
the
basic
processor aborts
execu-
tion
of
the
BA
L and traps to
location
X'4C'
with register R
changed
to
the
updated
instruction address.
92
Call
Instruct; ons
CALL
INSTRUCTIONS
Each of
the
four
CALL
instructions causes
the
basic processor
to
trap
to
a
specific
location
for
the
next
instruction in
se-
quence.
The four
CALL
instructions,
their
mnemonics,
and
the
locations to
wh
i ch
the
basi c processor traps
are:
Instruction
Trap
Name
Mnemonic
Location
CALL
1
CAll
X'48'
CALL
2 CAL2
X'49'
CALL
3
CAL3
X'4A'
CALL
4
CAL4 X'4B'
Each
of
these four
trap
locations must
contain
an
EXCHANGE
PROGRAM
STATUS
WORDS (XPSD) instruction. Execution
of
XPSD
in
the
trap
location
for a
CA
lL instruction
is
de-
scribed
under "Control Instructions,
XPSD
Exchange Pro-
gram Status Words".
If
the
XPSD
instruction is coded with
bit
position 9
set
to 1,
the
next
instruction
(executed
after
the
XPSD) is
taken
from
one
of
16
possible
locations,
as
designated
by the
value
in
the
R field of the
CALL
instruc-
tion.
Each
of
the
16
locations may
contain
an
instruction
that
causes
the
basic processor to branch
to
a
specific
routine;
thus,
the
four
CALL
instructions can be used to
enter
any
of
as many
as
64
unique routines.
The
effective
address of
either
a
direct
or
indirect
CALL
instru ction
is
not used for a memory referen
ce
and I
there-
fore,
cannot
cause a
trap.
CALI
CALL
1
(Word index
alignment)
CALL
1 causes
the
basic
processor
to
trap
to
location
X'48'.
CAL2
CALL
2
(Word
index
alignment)
CALL
2 causes
the
basic processor to
trap
to
location
X'49'.
CAL3
CA.LL
3
(Word index alignment)
6 7 8
CA
LL
3 causes
the
basi c processor to trap to
location
X
'4A',
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