The
POLR
instruction
also
resets
and
clears
this
unit's
Processor
Fault
Interrupt signal
and
the
error status
regis-
ter. In
addition
to
the
operation
code
of
X'4F',
bits 15,
16, and 17 must be coded as
011,
respectively.
Affected: (R),
CC1, CC2,
CC3
Condition
code
settings for
the
POLR
instruction
are:
1 2 3 4 Result of
POLR
o 0 0 - Processor
fault
interrupt
not
pending.
o 0 - Processor
fault
interrupt
pending.
o 1 - Pari ty error
detected
on
returned
status
and/or
condition
code.
The result
of
the
POLR
is
indeterminate.
1 1 0 - Unit address not
recognized.
AID
ACKNOWLEDGE INPUT/OUTPUT
INTERRUPT
(Word
index
alignment,
privileged)
ACKNOWLEDGE INPUT/OUTPUT
INTERRUPT
is used
to
acknowledge
an
input/output
interrupt
and
to
identify
the
I/o
subsystem (processor,
device
controller,
device)
that
is causing
the
interrupt
and why.
If
more
than
one
I/O
subsystem has'
an
interrupt
pending,
only
the
subsystem
with
the
highest priority will respond
to
the
AIO.
Bits
18-
23
of
the
effective
virtual address of
the
AIO
instruction
(normally used to specify
the
cluster
and
unit
addresses
of
the
I/o
address field) must be
coded
000000
to
specify
the
standard
I/O
system
interrupt
acknowledgment
{other
codings of
these
bits
are
reserved for use with special
I/o
systems}. The remainder of
the
I/O
selection
code
field
{bit positions 24-31}
are
not used in
the
standard
I/o
in-
terrupt
acknowledgment
(the address of
the
interrupt source
is a
part
of
the
response from
the
standard
I/o
system
to
the
AIO
instruction).
Standard
I/O
interrupts
are
program
controlled
via
the
con-
trol flags
(IZC,
ICE, IUE,
HTE,
and
SIL)
within
the
I/O
command doublewords (lOCDs)
that
comprise
the
command
list for
the
I/o
operation.
If
a
particular
flag is
coded
as
a 1
and
if
the
corresponding
condition
occurs
within
the
I/O
operation,
then
an
I/o
interrupt
is requested
(e.
g.
,
if
the
IZC flag is set
to
1
and
if
the
byte
count
for
the
I/O
operation
has
been
decremented
to
zero,
then
an
I/O
interrupt
is requested by
that
I/O
subsystem to
indicate
the
end
of
that
I/o
operation; if
the
IZC
flag is
coded
as a
0,
no
I/o
interrupt
is requested as a result of
the
byte
count
bei ng
decremented
to
zero).
If
two or more flags
are
coded
to
cause
an
interrupt
for two
or more
conditions,
an
interrupt
is requested whenever
any
of
the
IIflagged
ll
conditions
is
detected.
For some
conditions
(transmission errors,
incorrect
length),
two or more flags must
be
properly
coded
(see
Chapter
4
for further
detai
Is
on IOCDs).
Some
error
conditions
{e.
g.,
pority
error on
reading
command
doubleword) will
unconditionally
cause
an
I/o
interrupt.
The various
conditions
which
may result in
an
I/O
inter-
rupt,
the
coding
of
the
corresponding control flags
within
the
IOCD,
and
the
bit
position
within
the
status word
(re-
turned
to
register
R)
that
indicates
the
presence
(1) or
ab~
sence
(0) of
that
interrupt
condition
are
listed
below:
Control Flags
Status
Condition
Coding Bit
Set
Zero
byte
count
IZC = 1
10
Channel
end ICE = 1
11
Transmission memory error
IUE
= 1,
HTE
= 1 12
Write
lock
violation
IUE
= 1,
HTE
= 1
12
Incorrect
length
IUE
= 1,
HTE
= 1
8,
12
and
SIL
= 0
Memory address error,
) (no flog
needed)
lOP
memory error,
lOP
control error, or 12
device
connection
address
parity
error
Transmission
data
error
iUE
=
i,
HTE
= i
9,
i2
Unusual end
IUE
= 1
12
lOP
halt
IUE
= 1
12, 14
Interrupts may
also
be
requested
by
certain
I/o
devices
when
they
execute
specific
orders {e.
g.,
when a
magnetic
tape
unit
executes
a Rewind
and
Interrupt order}. Refer
to
the
applicable
peripheral
reference
manual for further
details.
When a
device
interrupt
condition
occurs,
the
lOP
forwards
the
request
to
the
interrupt
system
I/o
interrupt
level.
If
this
interrupt
level is
armed,
enabled,
and not
inhibited,
the
BP
eventually
acknowledges
the
interrupt
request
and
executes
the
XPSD
instruction
in main memory
location
X'5C',
which normally leads
to
the
execution
of
an
AIO
i nstructi on.
For
the
purpose of
acknowledging
standard
I/O
interrupts,
the
lOPs,
device
controllers,
and
devices
are
connected
in
a preestablished
priority
sequence
that
is customer-assigned
and
is
independent
of
the
physical
locations
of
the portions
of
the
I/O
system in a
particular
installation.
If
the
R field of
the
AIO
instruction
is
0,
the
condition
code
is
set
but
the
general
register
is not
affected.
Input/Output
Instructions 123
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