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Xerox 550 User Manual

Xerox 550
188 pages
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Designation
Function
EI
(cont. )
allowed
to
occur.
The
function
of
these
group
interrupt
inhibits
are
described
in
"Centra
1-
ized
Interrupt
System",
later
in this
chapter.
A master mode
or
master-protected
mode
pro-
gram
can
change
the
group
interrupt
inhibits
by
executing
an
LPSD, XPSD, PSS, PLS,
or
WRITE
DIRECT
0ND)
instruction.
These
priv-
i
leged
instructions
are
described
in
Chap-
ter
3,
"Control
Instructions".
RP
Register
pointer.
This
2-bit
field
selects
one
of
the
4 possible blocks
of
general-purpose
registers as
the
current
register
block.
A
master or
master-protected
mode program
can
change
the
register
pointer
by
executing
LPSD,
XPSD, PSS,
PLS,
or
the
LOAD REG-
ISTER
POINTER
(LRP)
instruction.
LRP
is
described
in
Chapter
3, under "Control
Instructions" .
RA
Register
altered
bit.
When a
trap
occurs,
this
bit
is
set
to
one
when
any
general
reg-
ister
or
location
in memory has
been
altered
in
the
execution
or
partial
execution
of
the
instruction
that
caused
the
trap.
MA Mode
altered.
This
bit
is
used to invoke both
the
master-protected
mode
of
operation
and
the
real-extended
addressing mode). Table 1
details
the
function
of
the
setting
of this
bit
in
conjunction
with
the
setting
of
the
MS
(bit
8)and
MM (bit 9)
fields.
The bits
are
set
by
an
LPSD,
XPSD, PSS, or
PLS
instruction.
MP Memory
protection
violation
address.
If
the
X
PSD
instruction
is
being
executed
in a
trap
routine
as
a result
of
a memory
protection
violation
and
the
SP
bit
in theXPSD
is
a
one,
the
effective
virtual
address causing
the
violation
is stored in
the
fourth
word.
This
storage
may
be
invoked
so
that
memory
pro-
tection
violations
can
be
recorded.
CENTRALIZED
INTERRUPTS
The system
includes
a
single,
centralized
interrupt
feature.
~~,
I interrupts
are
terminated in the System Control Pro-
cessor.
The System Control Processor
is
described
earl
ier
and
also
in
Chapters
5
and
6.
When a
condition
that
will
result
in
an
interrupt
is
sensed,
a signal
is
sent
to
the
corresponding
interrupt
level.
If
that
level
is
"armed",
it
advances
to
the
waiting
state.
30
Centralized
Interrupts
When
all
the
conditions
for
acknowledging
the
interrupt
have
been
achieved,
the
basic
processor stops
executing
the
current
program
and
executes
the
instruction
in
the
cor-
responding
interrupt
location.
After
the
basic
processor has
successfully
accessed
the
interrupt
instruction,
it
advances
the
interrupt
level
to
the
active
state.
The
basic
processor
may
actually
execute
many program instructions
between
the
time
that
the
interrupt-requesting
condition
is
sensed
and
the
time
that
the
actual
interrupt
acknowledgment
oc-
curs.
After
the
interrupt
is
completely
processed,
the
basic
processor returns
to
the
interrupted
program
and
resumes its
execution.
STATES
OF
AN
INTERRUPT
LEVEL
An
interrupt
level
is
mechanized
by means
of
three
flip-
flops.
Two
flip-flops
are
used
to
define
four
mutually
ex-
clusive
~tates:
disarmed,
armed,
waiting,
and
active.
The
third
flip-flop
provides
the
disabled/enabled
function
and
is
independent
of
the
defined
state.
The various
states
and
the
conditions
of
interrupt
levels
are
described
in
the
fol-
lowing
paragraphs.
Figure
10
conceptually
illustrates
the
operational
state
changes
of
a
typical
interrupt
level.
DISARMED
When
an
interrupt
level
is
in
the
disarmed
state,
no
signal
is
admitted
to
that
interrupt
level;
that
is,
the
level
neither
accepts
nor remembers
an
interrupt
event,
nor
is
any
pro-
gram
interrupt
caused
by
it
at
any
time.
Although
an
interrupt
level
can
change
from
any
state
to
the
disarmed
state,
only
a
special
form
of
the
WRITE
DIRECT
instruction
(WD)
can
cause
a disarmed level
to
change
to
another
state.
The
WD
instruction
is
described
in
Chap-
ter
3, IIControl Instructions
II.
ARMED
When
an
interrupt
level
is
in
the
armed
state,
it
can
accept
and
remember
an
interrupt
signal.
The
receipt
of
such a
sig-
nal
advances
the
interrupt
level to
the
waiting
state
where
it
remains unti I
it
is
allowed
to
advance
to
the
active
state.
A
special
form
of
the
WD
instruction
can
cause
an
armed
level to
be
advanced
di
rectly
to
the
active
state.
A
level
can
change
from
any
state
to
the
armed
state.
WAITING
For
an
interrupt
level
to
be
in
the
waiting
state,
that
level
must
have
been
previously
armed
and
received
an
interrupt
signal.
The
signal
may
have
been
generated
externally,
internally,
or
have
resulted
from
a
WD
operation.
Any
signals
received
by
an
interrupt
level
already
in the
waiting
state
are
ignored.

Table of Contents

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Xerox 550 Specifications

General IconGeneral
Monthly Duty CycleUp to 300, 000 pages
ConnectivityEthernet, USB
Print Speed (Color)Up to 50 ppm
Duplex PrintingStandard
Printer TypeLaser
Supported Operating SystemsWindows, macOS, Linux
Paper SizeA4, Legal, Letter

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