2 3 4 Reason for abort
- Impending overflow of word count and
under-
flow
of
space count on a push operati on or
impending overflow
of
space count and
under-
flow
of
word count
on
a pull operation.
The
push-down stack limit trap was inhibited
by
both
the
TW
and
the
TS
bits.
If
a push-down instruction is successfully
executed,
CC1
and
CC3 are reset to 0
at
the
completion
of
the instruc-
tion. Also, CC2 and CC4
are
independently set to
indi-
cate
the current status
of
the
space
count and the word
count, respectively, as
follows:
2 3 4 Status
of
space and word counts
- 0 - 0 The current space count and the current word
count
are
both
greater
than zero.
- 0 -
The
current
space
count is
greater
than
zero,
but the current word count is zero, indicating
that
the
stack is
now
empty.
If
the next
op-
eration on
the
stack is a pull instruction,
the
instruction
wi
II
be aborted.
-
0
The
current word count is
greater
than
zero,
but the current space count
is
zero,
indi
cat-
ing
that
the
stack is now full.
If
the
next
op-
eration on
the
stack is a push instruction,
the
instruction
wi
II
be aborted.
If
the basic processor does not trap to location X
'
42
1
as a
result
of
impending stack limit overflow/underflow, CC2
nn~
("("4
in~ir.ntp
thp
c:tntlls
of
thf!
soace and word counts
--
••
- - - -
-----.
- -
--
- - I
at
the
termin~tion
of
the push-down instruction, regardless
of
whether the space and word counts were
actually
modi-
fied by the instruction.
In
the following descriptions
of
the push-down instructions, condition code settings given
are only those
that
can
be
produced by the instruction,
provided that the basi c processor does not trap to
lo-
cation X'421.
PSW
PUSH
WORD
(Doubleword index alignment)
PUSH
WORD
stores the contents
of
register R into
the
push-
down stack defined by the stack pointer doubleword
located
at
the
effective
doubleword address of
PSW.
If
the push
op-
eration can
be
successfully performed, the instruction
op-
erates as follows:
1.
The
current
top-of-stack
address
(SPD
15
_
31
)t is
incre-
mented by 1 to point to the new
top-of-stack
location.
2.
The
contents of register R
are
stored
in
the location
pointed to by
the
new
top-of-stack
address.
t For rea
I extended mode
of
addressi
ng
th
i
sis
a 20-bi t
field (12-31); for real and virtual addressing modes
it
is
a 17-bit field (15-31).
3.
The
space count (SPD33-47)
is
decremented by 1 and
the word count (SPD49-63) is incremented
by
1.
4.
The
condition code
is
set to
reflect
the new status
of
the space count.
Affected: (SPD), (TSA+1), CC Trap: Push-down stack
limit
(SPD)15_31 + 1 -
SPD
15
_
31
t
(R)
-
{SPD
15
_
31
)t
{SPD)33_47-
1
-
SPD
33
_
47
(SPD)
49-63
+ 1 -
SPD
49-63
Condition code settings:
2 3
4
Result
of
PSW
0 0
0
0 Space count
is
greater
}
than
O.
0
0
0 Space count
is
now
O.
0
0
0
Word count = 2
15
_1
,
TW
=
1.
0 0 Space count =
0,
TS
= 1.
0 Space count = 0, word
count
= 0,
TS
=
1.
0
Word count = 2
15
_1
,
space count = 0,
TW
= 1, and
TS
=
1.
PLW
PULL
WORD
(Doubleword index alignment)
Instruction
completed
Instruction
aborted
PULL
WORD
loads register R with the word currently
at
the
top
of
the push-down stack defined by the stack pointer
doubleword located
at
the effective doubleword address
of
PLW.
If
the pull operation can be performed successfully,
the instruction operates as follows:
1.
Register R is loaded with the contents
of
the
loca-
tion pointed
to
by the current
top-of-stack
address
{SPD
1
5-31)t.
2.
The
current
top-of-stack
address
is
decremented by 1,
to point to the new
top-of-stack
location.
t
For
real extended mode
of
addressing this is a
20-bit
field (12-31); for real and virtual addressing modes
it
is
a
17-bit
field (15-31).
Push-Down Instructions
(Non-Privileged)
81
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