If
CC4
= 1,
the
MIOP is in the
test
mode
and
the meaning
of the
condition
code
during
an
HIO is:
2 3 4 Meaning
000
Unit is performing
an
Order
Out
operation.
010
Unit is performing
an
Order
In
operation.
o 0 Unit
is
performing a Data
Out
operation.
o 1
o
RIO
Processor
Interface
detected
parity error on
re-
turned status
and/or
condition
code.
The
re-
sult of the
HIO
is indeterminate.
Unit is performing a Data In operation.
BCF
detected
whi Ie unit performing a Data
In
operation.
RESET
INPUT/OUTPUT
0/'Iord
index
alignment,
t privileged)
RESET
INPUT/OUTPUT causes the
selected
lOP
to
generate
an
I/O
reset signal
to
all
devices
attached
to
it.
In
addi-
tion
to
the operation
code
X'4f!,
bits 15, 16, and 17 must
be
coded
as
001,
respectively.
An
RIO
instruction resets
the
selected
unit in the same
manner as
ZCRIO on
the
operator's
control console. How-
ever,
unlike
the
control command, the
RIO
instruction
resets only
the
addressed unit and may be
controlled
by
the
executing
program. Since
the
BP
may be addressed as
an
lOP,
it
wi
II
accept
an
RIO instruction
that
causes
the
BP
to reset itself in the same manner as
ZCRBP.
(Note
that
this procedure
is
not normal
practice.)
Cluster addresses (CA),
bit
positions
18-20,
may
have
values
of
X'O'-X'7'.
Cluster addresses
X'0'-X'6'
may
be
assigned
to
any
cluster
containing
processors (i.
e.,
-BP
and
MIOP). In a monoprocessor system,
cluster
address
X'O' is assigned to
the
cluster
containing
the
basic
pro-
cessor
(BP).
Cluster address
X'7'
is assigned only
to
the
cluster
containing
a system processor.
If
CA equals
X'7',
the
UA
field is reserved. Unit addresses (UA),
bit
posi-
tions
21-23,
may
have
values
of
X'O'-X'?'.
Unit
ad-
dresses
are
required only
if
the
cluster
address
is
X 'O'.;.X'6'
(i
.e.,
cluster
contains
either
a
BP
and/or
MIOP).
Unit
addresses
X'O'-X'5'
may be assigned to processors within
the
cluster.
Unit address
X'5',
in cluster X'O'
is
re-
served for
the
BP.
Unit address
X'6'
is
assigned always
to
the
Ml
and
~mit
address
X'7'
is assigned always to
the
PI
for a
II
cI
usters.
Status information is returned only in
the
condition
code
bits. The R field is not used.
Affected:
CC 1,
CC2,
CC3
122
Input/Output
Instructions
Condition
code
settings
are
as shown below:
2 3 4 Meaning
o 0 0 -
I/O
address
recognized.
1 0 1 - Parity error
detected
on returned status
and/or
condition
code.
The result of the
RIO
is
indeterminate.
1 1 0 -
I/O
address not
recognized.
POLP
POLL
PROCESSOR
0/'Iord
index alignment, t privileged)
POLL
PROCESSOR causes
the
addressed unit to return unit
fau
I t status in
bi
ts 16-31 of reg i ster Rtt.
Th
i s status i
nfor-
mation is unit
dependent
(see Appendix
C,
Table
C-l).
In
addition
to the
operation
code
of
X'4F',
bits 15, 16,
and 17 must be
coded
as
010,
respectively.
Affected: (R),
CC1,
CC2, CC3
Condition
Code
settings
are
as shown below:
1 2 3 4 Result of
POLP
o 0 0 - Processor
fault
interrupt not pending.
o 1 0 - Processor
fault
interrupt pending.
1
0 1 - Pari ty error
detected
on returned status
and/or
condition
code.
The result of
the
POLP is
indeterminate.
1 1 0 - Unit address not
recognized.
POLR
POLL
AND
RESET
PROCESSOR
(Word index alignment, t privileged)
POLL
AND
RESET
PROCESSOR causes the
selected
unit to
return unit
fault
status in bits
16
to
31
of register
Rtt
and
resets
the
unit's
fault
status register. This status informa-
tion is unit
dependent
(see Appendix C, Table
C-1).
t See footnote
to
HIO instruction.
tt
This
fault
status
is
duplicated
in bits 0
to
15
of register
R.
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