Xerox 550 User Manual

Designation Function
CC
FR
FS
FZ
FN
Condition code. This generalized 4-bit code
indicates the nature of the results of an
instruction. The significance of the condition
code bits depends upon the particular instruc-
tion just executed. After an instruction is
executed, the BRANCH ON CONDITIONS
SET (BCS) and BRANCH ON CONDITIONS
RESET (BCR) instructions can be used singly
or in combination to test for a particular con-
dition code setting. (These instructions are
described in Chapter 3, "Execute/Branch
Instructi ons ").
In some operations only a portion of the con-
dition code is involved; thus, the term CCl
refers to the first bit of the condition code,
CC2 to the second bit, and CC3 and CC4,
respectively, to the third and fouTth bits.
Any program can change the current value
of the condition code by executing either
the LOAD CONDITIONS AND FLOATING
CONTROL IMMEDIATE (LCFI) or the LOAD
CONDITIONS AND FLOATING CONTROL
(LCF) instruction. Any program can store
the current condition code by executing
the STORE CONDITIONS AND FLOATING
CONTROL (STCF) instruction. These instruc-
tions are described in Chapter 3, II Load/Store
Instructions".
Floating round mode control (see FN below).
Floating significance mode control (see FN
below).
Floating zero mode control (see FN below).
Floating normalize mode control. The four
floating-point mode control bits (FR, FS, FZ,
and FN) control the operation of the basic
processor with respect to invoking the round-
off mode of floating-point calculations,
checking floating-point significance, gen-
erating zero results, and normalizing the
results of floating-point additions and sub-
tractions, respectively. (The floating-point
mode controls are described in Chapter 3,
II Floating-Point Instructions".) Any program
can change the state of the current floating-
point mode controls by executing either the
LCFI or the LCF instruction. Any program
De~gnaHon FuncHon
FN (cont.) can store the current state" of the current
floating-point mode controls by executing the
STCF instruction.
MS
MM
AM
IA
WK
CI
II
EI
Master/slave mode control. The basic pro-
cessor is in the master mode when this bit and
the mode altered bit (bit 61) both contain
zero; it is in the slave mode when this bit
contains one. (See MS for a description of
master-protected mode.) A master mode or
master-protected mode program can change
this mode control bit by executing the
LOAD PROGRAM STATUS WORDS (LPSD),
EXCHANGE PROGRAM STATUS WORDS
(XPSD),
PUSH STATUS (PSS), or PULL STATUS
(PLS) instruction. These privi leged instruc-
tions are described in Chapter 3, "Control
Instructions" •
Memory map control. The memory map is in
effect when this bit position contains a one.
A master mode or master-protected mode pro-
gram can change the memory map control by
executing an LPSD
,
XPSD
,
PSS, or PLS
instruction.
Arithmetic mask. The fixed-point arithmetic
overflow trap is permitted to occur when this
bit contains one. The instructions that can
cause fixed-point overflow are described in
the section "Trap System", later in this chap-
ter. The arithmetic trap mask can be changed
by a master mode or master-protected mode
program
executing an LPSD, XPSD, PSS , or
PLS instruction.
Instruction address. This 17-bit field contains
the virtual address of the next instruction to
be executed.
Write key. This field contains the 4-bit key
used in conjunction with a write lock in the
memory write protection feature. A master
mode or
master-protected mode program can
change the value of the write key by execu-
ting an LPSD
,
XPSD,
PSS , or PLS instruction.
Counter interrupt group inhibit (see El, below).
Input/output interrupt group inhibit (see El,
below).
External interrup group inhibit. The three in-
terrupt group inhibit bits (CI
,
II, and EI)
determine whether certain interrupts are
Main Memory 29

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