Note:
Since the same write key prevai
Is
for the
entire
lOCO and all memory locations within a mem-
ory page
are
assigned the same write lock, the
write
key/write
lock relationship may change
when the memory byte address is incremented
{or
decremented} across a memory page boundary.
3.
If
the order specifies an input operation
{e.
g.,
Read,
Read Backward, or Sense} and the
Skip flag is coded
as a 1,
all
parameters within. the
10CD,
except
the
write key, may be
applicable.
As
a result
of
receiving
an appropriate input order, the
device
transmits
data
{Read
or
Read Backward order}
or
information from
special registers (Sense order) into
the,data
buffers
within the
I/o
subchannel
of
the lOP. -Because the
Skip flag is coded as a 1, the
lOP
can
not
access main
memory (the write key may be ignored and a Write Lock
Violation can
not
occur). Although the
data
can
not
be stored in the main memory, the
lOP
increments the
memory byte address (except during a
Read
Backward
order, when
it
is decremented) and decrements the byte
count by one for
each
byte transferred
out
of
the
data
buffers.
The
devi
ce
may continue to transmit
data
into
the
data
buffers and the
lOP
may continue to update
the memory byte address and byte count unti
I
the
cur-
rent order
is
either
completed in a normal manner or
terminated because
of
an "unusual
end"
condition
(other than a Write
Lock
Violation).
4. If the order specifies an output operation (e.
g.,
Write
or
Control) and
if
the Skip flag
is
coded as a 0,
all
parameters within the
lOCO,
except
the
write
key,
may be
applicable.
When transferring
data
(Write
order) or information
(Control order)
out
of
main
mem~ry,
the write
key/write
lock
checking
is not
performed;
hence,
the write key may be ignored.
Likewise, a Write
Lock
Violation will
not
occur.
For
an
output
operation,
the lOP
wi
II
access main memory
{in
accordance
with the priority
that
prevai
Is
for
ac-
cessing main
memory}
and transfer up to four bytes
of
data
(or information), as specified by the
current
mem-
ory byte address, to the
data
buffers
of
the appropriate
I/O
subchannel.
The
lOP
also increments the memory
byte address and decrements the byte
count
by one for
each
byte
of
data
transferred. Data is then transferred
from
the
data
buffers to the devi
ceo
The
lOP
may
con-
tinue to
access
main memory, transfer up to four bytes
of
data
from
main memory to the appropriate
data
buf-
fers, and update
the
memory byte address and
byte
count. The
device
continues to
output
·data unti I the
order is
either
completed in a normal manner or
ter-
minated because
of
an "unusual end"
condition.
5.
If
the
order specifies
an
output operation (e.
g.,
Write
or
Control) and
if
the Skip flag is coded as a 1,
all
parameters within the current
lOCO,
except
the write
key, may be
applicable.
Because the Skip flag is
coded as a 1,
the
lOP
can not access main memory for
any
data
(or
information). Instead, the
lOP
generates
and loads zeros
(XIOOI)
into the
data
buffers
of
the
appropriate
I/o
subchannel and increments the memory
byte address and decrements the byte count by one for
each
byte loaded.
The
zeros
are
then transferred
from
the
data
buffer to the
device.
The
lOP
may continue
to
generate
and load zeros· into the
data
buffers and
update
the memory byte address and byte count,
ac-
cordingly, and the
device
may
continue
to
output
zeros
unti
I the order is
either
completed in a normal manner
or
terminated because
of
an "unusual
end"
condition.
DATA
CHAINING
An
order may
be
continued
from
the
current
operational
lOCO
to the
next
operational
lOCO,
if
data
chaining
is
specified
in the current
lOCO.
In this
case,
the
lOP
wi
II
automatically
fetch
the
next
operational
lOCO,
asdescribed
under "Fetching Phase", when the
byte
count
of
the current
lOCO
is
reduced to zero.
In
the process
of
fetching the
next
operational
lOCO,
the lOP may
fetch
and
execute
a
control
lOCO containing a Transfer in Channel command
without
affecting
the
continuity
of
the order. The process
of
fetching
and
loading the
next
operational
lOCO into the
control registers
of
the
I/O
subchannel is transparent to
the
device.
That is, the
device
continues to
operate
as
if
the
order were defined by a single
lOCO.
Also, any changes
in the status
of
the Skip flag
or
in the write key from one
lOCO to the
next
is transparent to the
device.
The
device
continues to
receive
zeros,
data,
or information from the
data
buffers during an
output
operation,
or continues to
transmit
data
(or information) into the
data
buffers regardless
of
whether
it
is subsequently
rejected
or stored whi
Ie
per-
forming an
input
operation.
During the
execution
phase,
an
I/o
interrupt may be
re-
quc5~cd
.such
time
th~
byt~
c~~:";~
cf
~!j
cpe:-~t:c~c!
!OCD
is reduced to zero
if
the Interrupt
at
Zero Byte Count (IZC)
flag is coded as a 1. Thus,
if
data
chaining
is
speCified,
the
lOP
may request an
I/O
interrupt without interfering
with
the
process
of
fetching the
next
operational
lOCO.
If the
I/o
interrupt level (location X
'
5C')
within the
inter-
rupt system is armed,
enabled,
and
not
inhibited,
the
I/O
interrupt may be processed by the
BP
in
accordance
with
the priority
that
prevai
Is
within the interrupt system, the
lOPs, and the
device
controllers
connected
to the lOP.
The
order may be completed in a normal manner when the
Data
Chain flag
of
the current
lOCO
(the last
10CD
of
a
logical record)
is
coded as a
O.
COMMAND
CHAINING
An
I/o
operation
may be continued from the current lOCO
to the next IOCD if command
chaining
is specified in
the
current
IOCD. Command
chaining
is commonly specified
when reading (or writing)
consecutive
records
of
data
from
the same
fi
Ie.
In
which
case,
the
current
IOCD must be
the last
IOCD for the current record and the
next
10CD
must
be
the first lOCO
of
the
next
logical record. Although
the
device
may
execute
the
same functional order for both
records,
logically,
it
is
equivalent
to two separate orders.
I/o
Operation
Phases 133
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