Xerox 550 User Manual

2. Bits 0-35, 60, and 61 of the current program status
words are unconditionally replaced by bits 0-35, 60,
and 61 of the second effective doubleword. The affected
portions of the program status words are:
Bit
Position
Designati on
Function
0-3
CC
Condi ti on code
4-7 FR, FS, FZ,
Floating control
FN
8
MS
Master/slave mode control
9
MM
Mapping mode
control
11
AM
Fixed-point arithmetic trap
mask
15-31
IA
Instructi
on address (real or
vi rtual)
32-35
WK
Write key
60
RA
Register altered
61
MA
Mode altered
3. A logical inclusive OR is performed between bits 37
through 39 of the current program status words and
bits 37 through 390f the second effective doubleword.
Bit
Position
Designation Function
37
CI Counter interrupt inhibit
38 II
I/O interrupt inhibit
39
EI
External interrupt inhibit
it any (or a i i) of bits 37, 38, or 39 of the second ef-
fective doubleword are O's, the corresponding bits in
the current program status words remain unchanged; if
any (or all) of bits 37, 38, or 39 of the second effec-
tive doubleword are l's, the corresponding bits in the
current program status words are set to l's. See "In-
terrupt System", Chapter 2, for a detailed discussion
of the interrupt inhibits.
4. If bit position 8 (LP) of XPSD contains a 1, bits 58
and 59 (register pointer) of the current program status
words are replaced by bits 58 and 59 of the second
effective doubleword; if bit 8 of XPSD is a 0, the cur-
rent register pointer value remains unchanged.
Affected: (EDL), (PSWs)
If (I) 10 = 1, trap or interrupt instructions only, effective
address is subject to current active addressing mode.
96 Controi Tnstructions
If (I) 10 = 0, trap or interrupt instructions only, effective
address is independent of current active addressing mode.
PSD - EDL
ED2
0
_
3
-CC; ED24_7 - FR,FS,FZ,FN
ED28 - MS; ED29 - MM
ED211 - AM;
ED
15
_
31
- IA
ED232-35 - WK
ED2
37
_
39
u CI,II,EI - CI,II,EI
If (1)8 = 1, ED2
58
_
59
- RP
If (1)8 = 0, RP not affected
If nonexistent instruction, 1 - CC 1 then, if (1)9 = 1,
IA+8-IA
If nonexistent memory address, 1 - CC2 then, if
{I)9 = 1, IA + 4 - IA
If privileged instruction violation, 1 - CC3 then, if
(1)9 = 1, IA + 2 - IA
If memory protection violation, 1 - CC4 then, if {I)9 = 1,
IA + 1 - IA
If CALL instruction, CC u CALL
8
_
11
- CC then, if
{I)9 = 1, IA + CALL
8
_
11
- IA
If (1)9 = 0, IA not affected
If watchdog timer, parity error, or instruction exception
trap, ED2
0
_
3
u TCCl-4 -CCl-4 then, if (1)9= 1,
IA + TCCl-4 - IA
LRP LOAD REGISTER POINTER
(Word
index alignment, privileged)
LOAD REGISTER POINTER loads bits 24-27 of the effective
word into the register pointer {RP} portion of the current
program status words. Bit positions ° through 23 and 28
through
31 of the effective word are ignored, and no other
portion ofthe program status words is affected. If the LOAD
REG ISTER POINTER instruction attempts to load the register
pointer with a vaiue that points to a nonexistent biock of
general registers, the basi c processor traps to location X'4D'.
Affected: RP
T rap: Instruction exception
EW
24
_
27
-
RP

Xerox 550 Specifications

General

Monthly Duty Cycle	Up to 300, 000 pages
Connectivity	Ethernet, USB
Print Speed (Color)	Up to 50 ppm
Duplex Printing	Standard
Printer Type	Laser
Supported Operating Systems	Windows, macOS, Linux
Paper Size	A4, Legal, Letter