General Procedures and Information
PHASER 3124 / PHASER 3125 09/06 6-15
• CPU Core : ARM1020E
32KB instruction cache and 32KB data cache
• Operating Frequency
CPU Core : over 300MHz
System Bus : 100MHz
•SDRAMC
32Bits Only, 100MHz
5 Banks (Up to 128MB per Bank)
•ROMC
4 Banks (Up to 16MB per Bank)
•IOC
6 Banks (Up to 16MB per Bank
•DMAC
4 Channels
•HPVC
Dual/Single Beam
LVDS Pad(VDO, HSYNC)
•UART
5 Channels (1 Channels Supports DMA Operation)
• PCI Controller
32Bits, 33/66MHz
PCI local bus specification rev2.2 Complaint
Host / Agent Mode (Supports 4 devices in host mode)
• NAND Flash controller
8/16Bits, H/W EEC generation
Auto boot mode (Using Internal SRAM, 4KB)
•MAC
10M/100Mbps
Full IEEE 802.3 Compatibility
• Engine Controller
LSU interface unit
Step Motor : 2 Channels
PWM : 8 Channels
ADC : 6 Channels
• I2C Controller
I2C(S-BUS) Slave device support(I2C Version 2.1)
•RTC
RTC Core Voltage : 3V
•PLL
3 PLL : MAIN, PCI, PVC
• Flash Memory :
Capacity : 8MB
Random Access Time : 10 us (Max)
Serial Page Access Time : 50ns (Min)
• DRAM : Capacity : 32MB (STD/MAX)
Type : SDRAM 100MHz/133MHz, 16bit
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