MutliLINX
™
Cable
Hardware User Guide 2-5
RST Reset —Pin used to reset internal
FPGA logic. Connection to this
pin is optional during configura-
tion.
During configuration, a Low
pulse causes XC3000A devices to
restart configuration.
After configuration, this pin can
driveLowtoresettargetFPGA
internal latches and flip-flops.
RST is the active high for
XC4000/XC5200 devices.
RT Read Trigger —Pinusedto
initiate a readback of target
FPGA.
MultiLINX output. Hardware
Debugger provides
Low-to-High transition on RT to
initiate readback.
RD (TDO) Read Data — MultiLINX input.
Hardware Debugger receives the
readback data through the RD
pin after readback is initiated.
Pin used to initiate a readback of
target FPGA.
TDO is for JTAG.
TRIG System Trigger —MultiLINX
input
High on this pin signals the
MultiLINX electronics to initiate
a readback and causes the RT pin
to go High.
Table 2-2 MultiLINX Pin Descriptions
Signal Name Function
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