Xilinx MultiLINX Series - Page 84

Hardware User Guide
3-22 Xilinx Development System
J1–5 N.C.
b
J1–6 TRIG XChecker Cable input
that allows an external
event to trigger read-
back of the XC3020A
or outputting a burst
of clocks to the
XC3020A.
Connects to tiepoint
J3–1.
J1–7
a
CCLK Provides clock
during configura-
tion or readback.
Connects to
XC3020A input pin
50.
J1–8 N.C.
b
J1–9
a
D/P Starts configuration
and indicates
completion.
Connects to
XC3020A DONE/
PROGRAM pin 45.
J1–10 N.C.
b
J1–11
a
DIN Provides configura-
tion data during
configuration.
Connects to
XC3020ADINinput
pin 58.
J1–12 N.C.
b
J1–13 N.C.
b
J1–14 N.C.
b
Table 3-7 XChecker/Parallel Cable III Connector J1
Pin Name Function Pin Name Function