Xilinx VC709 - Page 34

34 www.xilinx.com VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
Chapter 1: VC709 Evaluation Board Features
PCIE_RX1_N AA5 B20 PETn1
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y22
PCIE_RX2_P AB4 B23 PETp2
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y21
PCIE_RX2_N AB3 B24 PETn2
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y21
PCIE_RX3_P AC6 B27 PETp3
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y20
PCIE_RX3_N AC5 B28 PETn3
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y20
PCIE_RX4_P AD4 B33 PETp4
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y19
PCIE_RX4_N AD3 B34 PETn4
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y19
PCIE_RX5_P AE6 B37 PETp5
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y18
PCIE_RX5_N AE5 B38 PETn5
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y18
PCIE_RX6_P AF4 B41 PETp6
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y17
PCIE_RX6_N AF3 B42 PETn6
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y17
PCIE_RX7_P AG6 B45 PETp7
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y16
PCIE_RX7_N AG5 B46 PETn7
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y16
PCIE_TX0_P W2 A16 PERp0
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y23
PCIE_TX0_N W1 A17 PERn0
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y23
PCIE_TX1_P AA2 A21 PERp1
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y22
PCIE_TX1_N AA1 A22 PERn1
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y22
PCIE_TX2_P AC2 A25 PERp2
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y21
PCIE_TX2_N AC1 A26 PERn2
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y21
Table 1-10: PCIe Edge Connector Connections (Cont’d)
Net Name FPGA (U1) Pin
PCIe Edge
Connector (P1)
Function FFG1761 Placement
Pin Name