Xilinx VC709 User Manual

VC709 Evaluation Board www.xilinx.com 35
UG887 (v1.0) February 4, 2013
Feature Descriptions
PCIE_TX3_P AE2 A29 PERp3
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y20
PCIE_TX3_N AE1 A30 PERn3
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y20
PCIE_TX4_P AG2 A35 PERp4
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y19
PCIE_TX4_N AG1 A36 PERn4
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y19
PCIE_TX5_P AH4 A39 PERp5
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y18
PCIE_TX5_N AH3 A40 PERn5
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y18
PCIE_TX6_P AJ2 A43 PERp6
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y17
PCIE_TX6_N AJ1 A44 PERn6
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y17
PCIE_TX7_P AK4 A47 PERp7
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y16
PCIE_TX7_N AK3 A48 PERn7
Integrated Endpoint block
transmit pair
GTHE2_CHANNEL_X1Y16
PCIE_CLK_Q0_P AB8 A13 REFCLK+
Integrated Endpoint block
differential clock pair
from PCIe
MGT_BANK_115
PCIE_CLK_Q0_N AB7 A14 REFCLK-
Integrated Endpoint block
differential clock pair
from PCIe
MGT_BANK_115
PCIE_PRSNT_B J49 2, 4, 6 A1 PRSNT#1
J49 Lane Size Select
jumper
NA
PCIE_WAKE_B AV33 B11 WAKE#
Integrated Endpoint block
wake signal
U1 FPGA Bank13 Pin AV33
PCIE_PERST_B AV35 A11 PERST
Integrated Endpoint block
reset signal
U1 FPGA Bank13 Pin AV35
Table 1-10: PCIe Edge Connector Connections (Cont’d)
Net Name FPGA (U1) Pin
PCIe Edge
Connector (P1)
Function FFG1761 Placement
Pin Name

Xilinx VC709 Specifications

General

Brand	Xilinx
Model	VC709
Category	Motherboard
Language	English