Xilinx VC709 User Manual

40 www.xilinx.com VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
Chapter 1: VC709 Evaluation Board Features
Note: The six control/status signals to/from each SFP+ connector are routed through a level shifter.
USB-to-UART Bridge
[Figure 1-2, callout 13]
The VC709 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44)
which allows a connection to a host computer with a USB port. The USB cable is supplied
in the VC709 evaluation kit (type-A end to host computer, type mini-B end to VC709 board
connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when
the USB cable is plugged into the USB port on the VC709 board.
Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send
(RTS), and Clear to Send (CTS).
AB41 SFP1_TX_DISABLE 3 TX_DISABLE
SFP+ Module 2 (P2)
AA39 SFP2_TX_FAULT 2 TX_FAULT
AA42 SFP2_MOD_DETECT 6 MOD_ABS
AB38 SFP2_RS0 7 RS0
AB39 SFP2_RS1 9 RS1
AA40 SFP2_LOS 8 LOS
Y42 SFP2_TX_DISABLE 3 TX_DISABLE
SFP+ Module 3 (P4)
AA41 SFP3_TX_FAULT 2 TX_FAULT
AC39 SFP3_MOD_DETECT 6 MOD_ABS
AD42 SFP3_RS0 7 RS0
AE42 SFP3_RS1 9 RS1
AD38 SFP3_LOS 8 LOS
AC38 SFP3_TX_DISABLE 3 TX_DISABLE
SFP+ Module 4 (P5)
AE38 SFP4_TX_FAULT 2 TX_FAULT
AC41 SFP4_MOD_DETECT 6 MOD_ABS
AE39 SFP4_RS0 7 RS0
AE40 SFP4_RS1 9 RS1
AD40 SFP4_LOS 8 LOS
AC40 SFP4_TX_DISABLE 3 TX_DISABLE
Table 1-14: SFP+ Module Control and Status (Cont’d)
XCVX690T (U1) Pin Net Name
SFP+ Module
Pin Number Pin Name

Xilinx VC709 Specifications

General

Brand	Xilinx
Model	VC709
Category	Motherboard
Language	English