VC709 Evaluation Board www.xilinx.com 29
UG887 (v1.0) February 4, 2013
Feature Descriptions
See the Silicon Labs Si5324 data sheet for more information on this device (Silicon Labs:
w
ww.silabs.com).
Memory Clock (SYSCLK_233_P and SYSCLK_233_N)
[Figure 1-2, callout 27]
The VC709 board has a LVDS 233.3333 MHz oscillator (U13) soldered onto the back side of
the board and wired to an FPGA MRCC clock input on bank 32. This 233.3333 MHz signal
pair is named SYSCLK_233_P and SYSCLK_233_N. The P and N signals are connected to
FPGA U1 pins AY18 and AY17 respectively.
• Oscillator: Si Time SIT9122AC-2D3-25E233.333333 (233.3333 MHz)
• PPM frequency jitter: 50 ppm
• Differential output
The LVDS termination resistor R43 is located within the FPGA via matrix on the bottom of
the board, and is not populated.
X-Ref Target - Figure 1-11
Figure 1-11: Jitter-Attenuated Clock
UG887_c1_11_090612
R16
4.7KΩ 5%
SI5324_VCC
Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
VDD3
GND
XB
XA
NC5
32
6
30
29
28
U24
CKOUT1_N
7
33
CKOUT1_P
C31
0.1μF 25V
X5R
C32
0.1μF 25V
X5R
SI5326_XTAL_XA
GND2
GND1
XB
XA
X6
114.285 MHz
20 ppm
SI5326_OUT_C_N
SI5326_OUT_C_P
SI5326_OUT_N
SI5326_OUT_P
SI5326_XTAL_XB
GND
NC4
2
1
3
4
C33
0.1μF 25V
X5R
C34
0.1μF 25V
X5R
REC_CLOCK_P
REC_CLOCK_N
REC_CLOCK_C_P
REC_CLOCK_C_N
16
17
R167
100Ω
CKIN1_P
CKIN1_N
NC
NC
12
13
CKIN2_P
CKIN2_N
10
5
VDD2
VDD1
14
NC3
9
NC2
2
NC1
NC
NC
NC
NC
NC
35
34
NC
NC
CKOUT2_P
CKOUT2_N
SI5326_INT_ALM 3
NC 4
NC 11
NC 15
NC 18
19
20
SI5326_RST1
21
31
GND2
9
GND1
31
A2_SS
31
A1
24
A0
22
SI5326_SCL
SCL
23
SI5326_SDA
SDA_SDO
27
NC
SDI
36
CMODE
GND
GND4
GND3
LOL
RATE1
RATE0
C2B
INT_C1B
CS_CA
RST_B
37
GNDPAD
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