Xilinx VC709 - Page 28

28 www.xilinx.com VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
Chapter 1: VC709 Evaluation Board Features
GTH SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N)
[Figure 1-2, callout 8]
The VC709 board includes a pair of SMA connectors for a GTH clock wired to GTH Quad
bank 113. This differential clock has signal names SMA_MGT_REFCLK_P and
SMA_REFCLK_N, which are connected to FPGA U1 pins AK8 and AK7 respectively.
Figure 1-10 shows this AC-coupled clock circuit.
• External user-provided GTH reference clock on SMA input connectors
• 1.8V differential input
Jitter-Attenuated Clock
[Figure 1-2, callout 9]
The VC709 board includes a Silicon Labs Si5324 jitter attenuator U24 on the back side of the
board. FPGA user logic can implement a clock recovery circuit and then output this clock
to a differential I/O pair on I/O bank 13 (REC_CLOCK_C_P, FPGA U1 pin AW32 and
REC_CLOCK_C_N, FPGA U1 pin AW33) for jitter attenuation. The jitter-attenuated clock
(Si5324_OUT_C_P, Si5324_OUT_C_N) is then routed as a reference clock to GTH Quad 113
inputs MGTREFCLK0P (FPGA U1 pin AH8) and MGTREFCLK0N (FPGA U1 pin AH7).
The primary purpose of this clock is to support CPRI/OBSAI applications that perform
clock recovery from a user-supplied SFP/SFP+ module and use the jitter-attenuated
recovered clock to drive the reference clock inputs of a GTH transceiver. The
jitter-attenuated clock circuit is shown in Figure 1-11.
X-Ref Target - Figure 1-10
Figure 1-10: GTH SMA Clock Source
SMA_MGT_REFCLK_C_P
J26
GND
J25
GND
UG887_c1_10_090612
SMA
Connector
SMA
Connector
SMA_MGT_REFCLK_C_N SMA_MGT_REFCLK_N
SMA_MGT_REFCLK_P
C25
C24
0.01 μF 25V
X7R
0.01 μF 25V
X7R