VC709 Evaluation Board www.xilinx.com 33
UG887 (v1.0) February 4, 2013
Feature Descriptions
PCI Express Endpoint Connectivity
[Figure 1-2, callout 11]
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application, 5.0 GT/s for a Gen2 application, and 8.0 GT/s for a Gen3 application.
The PCIe transmit and receive signal datapaths have a characteristic impedance of
85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7 series FPGAs GTH
transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX690T-2FFG1761CES FPGA (-2 speed grade) included with the VC709 board
supports up to Gen3 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and
the _N net is connected to pin AB7. The PCI Express clock circuit is shown in Figure 1-13.
PCIe lane width/size is selected through jumper J49 (Figure 1-14). The default lane size
selection is 1-lane (J49 pins 1 and 2 jumpered).
Table 1-10 lists the PCIe edge connector connections at P1.
X-Ref Target - Figure 1-13
Figure 1-13: PCI Express Clock
X-Ref Target - Figure 1-14
Figure 1-14: PCI Express Lane Size Select Jumper J49
UG887_c1_13_090612
PCI Express
Eight-Lane
Edge Connector
GND
GND
A15
A13
A14
P1
REFCLK+
A12
GND
C544
0.01μF 25V
X7R
C545
0.01μF 25V
X7R
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
PCIE_CLK_Q0_C_P
PCIE_CLK_Q0_C_N
OE
REFCLK-
UG887_c1_14_083112
PCIE_PRSNT_B
PCIE_PRSNT_X1
PCIE_PRSNT_X4
PCIE_PRSNT_X8
J49
1
3
5
2
4
6
Table 1-10: PCIe Edge Connector Connections
Net Name FPGA (U1) Pin
PCIe Edge
Connector (P1)
Function FFG1761 Placement
Pin Name
PCIE_RX0_P Y4 B14 PETp0
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y23
PCIE_RX0_N Y3 B15 PETn0
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y23
PCIE_RX1_P AA6 B19 PETp1
Integrated Endpoint block
receive pair
GTHE2_CHANNEL_X1Y22
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