Xilinx VC709 - Page 70

70 www.xilinx.com VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
Appendix C: Master UCF Listing
## SMA J31 (P)
## SMA J32 (N)
##
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NET USER_CLOCK_P LOC = AK34 ; # T1_MRCC_14
NET USER_CLOCK_N LOC = AL34 ; # T1_MRCC_14
NET USER_SMA_CLOCK_P LOC = AJ32 ; # T2_MRCC_14 SMA J31
NET USER_SMA_CLOCK_N LOC = AK32 ; # T2_MRCC_14 SMA J32
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##
## LVDS Clock Inputs
## Multi-region clock capable I/O
## Fixed frequency 200MHz and 233.33333 MHz
## AC coupled clock inputs
## IO Standard DIFF_SSTL15 or DIFF_SSTL15_DCI
## Banks 32 & 38 FPGA VCCO = 1.5V
##
## 233.33333MHz for 1866MT/s SODIMM (VC709)
## 200MHz for 1600MT/s SODIMM (VC707)
##
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NET SYSCLK_P LOC = H19 ; # T2_MRCC_38 200 MHz
NET SYSCLK_N LOC = G18 ; # T2_MRCC_38
NET SYSCLK_233_P LOC = AY18 ; # T2_MRCC_32 233.33333 MHz
NET SYSCLK_233_N LOC = AY17 ; # T2_MRCC_32
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##
## Silicon Labs SI5324 Clock IC U24
## FPGA Bank 13 VCCO = 1.8V
## Clock multiplier & jitter attenuator
## SI5324 is on the secondary I2C bus
## I2C @ 0x68 via PCA9548A 1:8 bus switch
##
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NET SI5324_INT_ALM_LS LOC = AU34 ; # See SI5324 datasheet
NET SI5324_RST_LS LOC = AT36 ; # SI5324 RESET (0 = reset)
NET REC_CLOCK_C_P LOC = AW32 ; # SI5324 CKIN1 input
NET REC_CLOCK_C_N LOC = AW33 ; # SI5324 CKIN1 input
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##
## CP2103 USB-to-UART Bridge
## USB Port J17
##
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NET USB_UART_CTS LOC = AR34 ; # CP2103 Clear to Send input
NET USB_UART_RTS LOC = AT32 ; # CP2103 Request to Send output
NET USB_UART_RX LOC = AU36 ; # CP2103 RX input UART TX output
NET USB_UART_TX LOC = AU33 ; # CP2103 TX output UART RX input
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