Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 133
UG074 (v2.2) February 22, 2010
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
R
RXNOTINTABLE_# Input Indicates non-existent 8B/10 code.
RXRUNDISP _# Input
Running disparity in the received serial data. When RXNOTINTABLE
is asserted in RXDATA, this signal becomes the ninth data bit.
RXCLKCORCNT[2:0]_# Input Status denoting the occurrence of clock correction.
SIGNAL_DETECT _# Input
Signal direct from PMD sublayer indicating the presence of light
detected at the optical receiver, as defined in IEEE Std 802.3, Clause 36.
If asserted High, the optical receiver has detected light. When
deasserted Low this indicates the absence of light.
If unused, this signal should be tied High to enable correct operation
the Ethernet MAC.
TXBUFERR_# Input TX buffer error (overflow or underflow).
CLIENTEMAC#DCMLOCKED Input
If a DCM is used to derive any of the clock signals going to the
Ethernet MAC, the locked port of the DCM must be connected to the
CLIENTEMAC#DCMLOCKED port of the Ethernet MAC. The
Ethernet MAC is held in reset until CLIENTEMAC#DCMLOCKED is
driven to logic 1.
If DCM is not used, tie this port to a logic 1.
DADDR Input Dynamic configuration address bus.
DO_# Output Configuration output data bus.
DRDY Output Strobe that indicates read/write cycle is complete.
DCLK Input Dynamic configuration bus clock.
DI_# Input Dynamic configuration input data bus.
DEN_# Input Dynamic configuration bus enable when set to a logic 1.
DWE_# Input Dynamic configuration write enable when set to a logic 1.
Table 4-6: 10/100/1000 SGMII and 1000BASE-X PCS/PMA Interface Signals (Cont’d)
Signal Direction Description
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English