Xilinx Virtex-4 User Manual

164 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 6: Use Models
R
Figure 6-3 shows how to integrate the Ethernet MAC with the LogiCORE Ethernet
Statistics block, where the LogiCORE Ethernet statistics counters are accessed via the DCR
bus. DS323
, LogiCORE Ethernet Statistics Data Sheet, provides a a full description of the
Ethernet Statistics LogiCORE block. Figure 6-3 illustrates how to connect LogiCORE
Ethernet Statistics blocks to both Ethernet MACs within the Ethernet MAC block. If
statistics are required for only one Ethernet MAC, then the multiplexing between the
statistics cores is simply replaced with a straight-through connection.
Figure 6-2: Statistics Register Read Timing
host_clk
HOSTRDDATA[8:0]
HOSTRDDATA[9]
HOSTRDDATA[15]
HOSTMIIMRDY
HOSTWRDATA[31:0]
LSW
UG074_4_02_112705
MSW
HOSTRDDATA[10]
EMAC I/O Pin Equivalent standalone
host bus signal
HOSTMIIMSEL
HOSTREQ
HOSTADDR[8:0]
HOSTADDR[9]
HOSTEMAC1SEL
HOSTRDDATA[31:0]
6 Clocks
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English