Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 31
UG074 (v2.2) February 22, 2010
Ethernet MAC Signal Descriptions
R
TIEEMAC#CONFIGVEC[53:0] — Configures the receive engine of the Ethernet MAC.
TIEEMAC#CONFIGVEC[53] Input
Receiver Reset. When this bit is
1, the receiver is held in reset.
This signal is an input to the reset circuit for the receiver block.
TIEEMAC#CONFIGVEC[52] Input
Receiver Jumbo Frame Enable. When this bit is 0, the receiver
does not pass frames longer than the maximum legal frame size
specified in IEEE Std 802.3-2002. When this bit is
1, the receiver
does not have an upper limit on frame size.
TIEEMAC#CONFIGVEC[51] Input
Receiver In-band FCS Enable. When this bit is
1, the Ethernet
MAC receiver passes the FCS field up to the client. When this bit
is 0, the Ethernet MAC receiver does not pass the FCS field. In
both cases, the FCS field are verified on the frame.
TIEEMAC#CONFIGVEC[50] Input
Receiver Enable. When this bit is
1, the receiver block is
operational. When this bit is 0, the block ignores activity on the
physical interface RX port.
TIEEMAC#CONFIGVEC[49] Input
Receiver VLAN Enable. When this bit is
1, VLAN tagged frames
are accepted by the receiver.
TIEEMAC#CONFIGVEC[48] Input
Receiver Half Duplex. When this bit is
1, the receiver operates in
half-duplex mode. When this bit is 0, the receiver operates in full-
duplex mode.
TIEEMAC#CONFIGVEC[47:0] Input
Pause frame Ethernet MAC Source Address[47:0]. This address is
used by the Ethernet MAC to match against the destination
address of any incoming flow control frames, and as the source
address for any outbound flow control frames.
The address is ordered for the least significant byte in the register
to have the first byte transmitted or received; for example, an
Ethernet MAC address of AA-BB-CC-DD-EE-FF is stored in byte
[47:0] as 0xFFEEDDCCBBAA.
Tied to the same Ethernet MAC address as
TIEEMAC#UNICASTADDR[47:0].
Notes:
1. A reset is needed before changes on TIEEMAC#CONFIGVEC[73] and [70:64] take effect.
Table 2-11: MAC Configuration Pins (Cont’d)
Signal Direction Description
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English