Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 33
UG074 (v2.2) February 22, 2010
Ethernet MAC Signal Descriptions
R
Table 2-14: PHY Data and Control Signals
Signal Direction Mode Description
PHYEMAC#MIITXCLK Input
10/100 MII
The TX clock generated from the PHY when
operating in 10/100 MII mode.
16-bit client
interface
used in
1000BASE-X
PCS/PMA
When the transmit client interface is configured
to be 16 bits wide, this is the clock input port for
the CLIENTEMAC#TXCLIENTCLKIN/2. See
“Transmit (TX) Client – 16-bit Wide Interface” in
Chapter 3.
EMAC#PHYTXCLK Output GMII
The TX clock out to the PHY in GMII 1000 Mb/s
mode only.
EMAC#CLIENTTXGMIIMIICLKOUT Output
GMII
The TX clock out to the PHY for GMII tri-speed
mode operation and RGMII.
RGMII
EMAC#PHYTXEN Output
10/100 MII
The data enable control signal to the PHY.
GMII
RGMII The RGMII_TX_CTL_RISING signal to the PHY.
EMAC#PHYTXER Output
10/100 MII
The error control signal to the PHY.
GMII
RGMII
The RGMII_TX_CTL_FALLING signal to the
PHY.
EMAC#PHYTXD[7:0] Output
10/100 MII
EMAC#PHYTXD[3:0] is the transmit data signal
to the PHY. EMAC#PHYTXD[7:4] are driven
Low.
GMII The transmit data signal to the PHY.
RGMII
EMAC#PHYTXD[3:0] is the
RGMII_TXD_RISING and EMAC#PHYTXD[7:4]
is the RGMII_TXD_FALLING signal to the PHY.
SGMII
The TX_DATA signal to the MGT.
1000BASE-X
PHYEMAC#RXCLK Input
10/100 MII
The recovered clock from received data stream
by the PHY.
GMII
RGMII
16-bit client
interface
used in
1000BASE-X
PCS/PMA
When the receive client interface is configured to
be 16 bits wide, this signal is the clock input port
for the CLIENTEMAC#RXCLIENTCLKIN/2.
See “Receive (RX) Client – 16-bit Wide Interface”
in Chapter 3.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English