Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 43
UG074 (v2.2) February 22, 2010
Client Interface
R
Back-to-Back Transfers
Back-to-back transfers can occur when the Ethernet MAC client is immediately ready to
transmit a second frame of data following completion of the first frame. In Figure 3-6, the
end of the first frame is shown on the left. At the clock cycle immediately following the
final byte of the first frame, CLIENTEMAC#TXDVLD is deasserted by the client. One clock
cycle later, CLIENTEMAC#TXDVLD is asserted High. This indicates that the first byte of
the destination address of the second frame is awaiting transmission on
CLIENTEMAC#TXD.
When the Ethernet MAC is ready to accept data, EMAC#CLIENTTXACK is asserted and
the transmission continues in the same manner as the single frame case. The Ethernet MAC
defers the assertion of EMAC#CLIENTTXACK to comply with inter-packet gap
requirements and flow control requests.
Figure 3-6: Back-to-Back Frame Transmission
ug074_3_08_063005
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXD[7:0]
CLIENTEMAC#TXDVLD
CLIENTEMAC#TXFIRSTBYTE
EMAC#CLIENTTXACK
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
DA SA
EMAC#PHYTXD[7:0]
(SGMII or 1000BASE-X
PCS/PMA only)
EMAC#PHYTXCHARISK
(SGMII or 1000BASE-X
PCS/PMA only)
EMAC#PHYCHARDISPMODE
(SGMII or 1000BASE-X
PCS/PMA only)
/T/ /R/ /S//I2//I2/ /I2/ /I2//I1/
FCS
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English