ZiLOG Z8 Technical Manual

Reset and Clock
letter u. Registers that are not predictable are
listed as undefined.
Program
execution starts four clock cycles after
RESET has returned High. The initial instruction
fetch is from location %C. Figure B-1 shows reset
timing.
After a reset, the first program executed should
be a routine that initializes the control regis-
ters to the required system configuration. The
Interrupt Request register remains inactive until
an EI instruction is executed. This guarantees
that program execution can proceed free from
interrupts.
RESET is the input of a Schmitt trigger circuit.
To form the internal reset line, the output of the
trigger is synchronized with the internal clock
(xtal frequency divided by 2). The clock must
therefore be running for RESET to function. For a
power-up
reset operation, the RESET input must be
held Low for at least 50 ms after the power supply
is within tolerance. This allows the on-board
clock oscillator to stabilize. An internal
pull-up combined with an external capacitor of
1 eF provides enough time to properly reset the Z8
(Figure 8-2).
R/W
Figure B-1.
8-2
B.2
CLOCK
The Z8 derives its timing from on-board clock
circuitry connected to pins XTAL1 and XTAL2. The
clock circuitry consists of an oscillator, a
divide-by-2 shaping circuit, and a clock buffer.
Figure 8-3 illustrates the clock circuitry. The
oscillator's input is XTAL1; its output is XTAL2.
The clock can be driven by a crystal, a ceramic
resonator, or an external clock source.
Crystals and ceramic resonators should have the
following characteristics to ensure proper oscil-
lator operation:
Cut: AT (crystal only)
Mode: Parallel, Fundamental
Output Frequency: 1 MHz - 12 MHz
Resistance:
100 ohms max
Depending on operation frequency, the oscillator
may require the addition of capacitors C1 and C2
(shown in Figure 8-4). The range of recommended
capacitance values is dependent on crystal speci-
fications but should not exceed 15 pF. The ratio
of the values of C1 to C2 can be adjusted to shift
the operating frequency of the circuit by approxi-
mately ±.005%.
Reset Tilling
FIRST MACHINE CYCLE
I
I- FIRST INSTRUCTION FETCH
I
3047-053

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English