ZiLOG Z8 Technical Manual

6.9 INSTRUCTION TIMING
The high throughput of the Z8 is due, in part, to
the use of instruct ion pipe lining, in which the
instruction fet.ch and execution cycles are over-
lapped. During the execution of an instruction
the opcode of the next instruction is fet.ched.
This is illustrated in Figure 6-10.
Figures 6-11 and 6-12 show typical instruction
cycle timing for instructions fetched from exter-
nal memory. (It should be noted that all instruc-
External Interface (Z8601,Z8611)
tion fetch cycles have the same machine timing
regardless of whether memory is internal or exter-
nal.) For those instructions that require execu-
tion time longer then that of the overlapped
fetch, or instructions that reference program or
data memory as part of their execut.ion, the pipe
must be flushed. In order to calculate the execu-
tion time of a program, the internal clock periods
shown in the cycles column of the instruction for-
mats in Section 5.4 should be added together. The
cycles are equal to one-half the crystal or input
clock rate.
I------------MACHINE CYCLE ------------1
T1 Tx
CLOCK
PO
~
P1
~
Ao-A7
X
0
0
-0
7
OUT
AS
~
OS
\~-----I
R/W
\
OM
~
J------------WRITE CYCLE------------
I'
figure 6-9b. Extended External Memory Write Cycle
3047-048 6-7

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English