ZiLOG Z8 Technical Manual

External Interface (ZB601,ZB611)
1··---T-1 ---- MACHI;2
E
CYCLE-
1
-·----
T
-
3
---'1
CLOCK
PO
·X
As-A15
X
P1
X
Ao-A7
)
(0
0
-0
7
IN)
C
'-----I
'----
\
I
R/W
7
C
X
X
I-
READ CYCLE
. I
Figure 6-6a. External Instruction Fetch, or Memory Read Cycle
6.6.1 Address Strobe (AS)
All transactions start with AS driven Low and then
raised High by the ZB. The rising edge of AS
indicates that R/W, DM, an9 the addresses output
from Ports a and 1 are valid. The addresses
output via Port 1 remain valid only during MnT1
and typically need to be latched using AS, whereas
Port a address outputs remain stable throughout
the machine cycle.
6.6.2 Data Strobe
The ZB uses 55 to time the actual data transfer.
For Write operations (R/W = Low), a Low on DS
indicates that valid data is on the Port 1 ADO-AD7
lines. For Read operations, (R/W = High), the
Address/Data bus is placed in a high-impedance
state before driving DS L6~ so that the addressed
device can put its data on the bus. The ZB sam-
ples this data prior to raising DS High.
6-4
6.6.3 External Memory Operations
Whenever the ZB is configured for external memory
operation, the addresses of all internal program
memory references appear on the external bus.
This should have no effect on the external system
since the bus control lines, 55 and R/W, remain in
their iriactive High state. DS and R/W become
active only during external memory references.
CAUTION
Do not use LDC, LDCI, LDE or LDEI to
wr ite to internal program memory. The
execution of these instructions causes
the ZB to assume that an external write
operation is being performed and this
will activate control signals 55 and
R/W.
3047·087

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English