Z8

ZiLOG Z8 Technical Manual

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Instruction

Set

CPU

Control

Instructions

Mnemonic

Operand

Instruction

CCF

Complement

Carry

Flag

01

Disable

Interrupts

EI

Enable

Interrupts

Nap

No

Operation

ReF

Reset Carry

Flag

SCF

Set

Carry

Flag

SRP

src

Set

Register

Pointer

5.2

PROCESSOR

FLAGS

The

Flag

register

(R252) informs

the

user

about

the

current

status

of

the

ZS.

The

flags

and

their

bit

positions

in

the

Flag

register

are

shown

in

Figure

5-1.

R252

FLAGS

Flag Register

(FCH;

Read/Write)

~~

LUSER

FLAG

F1

LUSER

FLAG

F2

HALF CARRY FLAG

DECIMAL ADJUST FLAG

OVERFLOW FLAG

'--------SIGN

FLAG

L..----------ZERO

FLAG

'--------------CARRYFLAG

Figure

5-1.

Flag

Register

The

ZS

Flag

register

contains

six

bits

of

status

information

which

are

set

or

cleared

by

CPU

opera-

tions.

Four

of

the

bits

(C,

V,

Z and

5)

can be

tested

for

use with

conditional

Jump

instruc-

tions.

Two

flags

(H,

D)

cannot be

tested

and

~re

used

for

BCD

arithmetic.

The

two

remaining

bits

in

the

Flag

register

(F1,

F2)

are

available

to

the

user,

but

they must be

set

or

cleared

by

instruction

and

are

not

usable

with

conditional

Jumps.

As

with

bits

in

the

other

control

registers,

Flag

register

bits

can be

set

or

reset

by

instructions;

however, only

those

instructions

that

do

not

affect

the

flags

as

an outcome

of

the

execution

should be used

(e.g.,

Load

Immediate).

5-2

5.2.1

Carry

Flag

(C)

The

Carry

flag

is

set

to

1 whenever

the

result

of

an

arithmet

ic

operation

generates

a

carry

out

of

or

a borrow

into

the

high

order

bit

7;

otherwise,

the

Carry

flag

is

cleared

to

O.

Following

Rotate

and

Shift

instructions,

the

Carry

flag

contains

the

last

value

shifted

out

of

the

specified

register.

An

instruction

can

set,

reset,

or

complement

the

Carry

flag.

RETI

changes

the

value

of

the

Carry

flag

when

the

saved

Flag

register

is

restored.

5.2.2

Zero

Flag

(Z)

For

arithmetic

and

logical

operations,

the

Zero

flag

is

set

to

1

if

the

result

is

zero;

otherwise,

the

Zero

flag

is

cleared.

If

the

result

of

testing

bits

in

a

register

is

0,

the

Zero

flag

is

set

to

1;

otherwise

the

flag

is

cleared.

If

the

result

of

a

Rotate

or

Shift

operation

is

0,

the

Zero

flag

is

set

to

1;

otherwise,

the

flag

is

cleared.

RET!

changes

the

value

of

the

Zero

flag

when

the

saved Flag

register

is

restored.

5.2.J

Sign

Flag

(S)

The

Sign

flag

stores

the

value

of

the

most

signif-

icant

bit

of

a

result

following

arithmetic,

logi-

cal,

Rotate,

or

Shift

operations.

When

performing

arithmetic

operations

on

signed

numbers,

binary

two's

complement

notation

is

used

to

represent

and

process

information.

A

positive

number

is

identified

by

a a

in

the

most

signifi-

cant

bit

position,

and

therefore,

the

Sign

flag

is

also

O.

A

negative

number

is

identified

by

a 1

in

the

most

significant

bit

position,

and

therefore,

the

Sign

flag

is

also

1.

RETl

changes

the

value

of

the

Zero

flag

when

the

saved

Flag

register

is

restored.

3047-072

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ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English

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