ZiLOG Z8 Technical Manual

External Interface (Z8601,Z8611)
1-------- MACHINE CYCLE --------1
CLOCK
PO
X
As-A15
X
P1
X
Ao-A7
X
Do-D7 OUT
X
LJ
'---
\
I
R/W
\
/
________ ~x~ ____________________ ~x~ __
'""I ,a--------- WRITE CYCLE --------1' I
Figure 6-6b. External Memory Write Cycle
6.7 SHARED BUS
Port 1, along with AS, DS, R/W, and Port 0 nibbles
configured as address lines, can be placed in a
high-impedance
state, allowing the Z8601 or the
Z8611 to share common resources with other bus
masters. This shared bus mode is under software
control and is programmed by setting Port 0-1 Mode
register bits D4 and D3 both to 1 (Figure 6-7).
Data transfers can be controlled by assigning, for
example, P3
3
as a Bus Acknowledge input and P34 as
a
Bus Request output. Bus Request/Acknowledge
control sequences must be software driven.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
P1
0
-P1
7
MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD7
11 = HIGH-IMPEDANCE ADo-AD7.
AS. OS. R/W. As-All. A12-A15
Figure 6-7. Shared Bus Operation
3047-088, 3047-004 6-5

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English