ZiLOG Z8 Technical Manual

10.4.2 Interrupt Mask Register (IHR)
Initialization
IMR (Figure 10-8) individually or globally enables
or disables the six interrupt requests. When bits
DO-OS are set to 1, the corresponding interrupt
requests are enabled. 07 is the master enable and
must be set before any of the individual interrupt
requests can be recognized. Resetting 07 globally
disables all of the interrupt requests. 07 is set
and reset by the EI and 01 instructions. It is
automatically reset during an interrupt machine
cycle and set following the execution of an
Interrupt Return (IRET) instruction.
NOTE
0
7
must be reset by the 01 instruction
before the contents of the Interrupt
Mask register or the Interrupt Priority
register are changed except:
• Immediately after a hardware .reset,
or
• Immediately after executing an inter-
rupt cycle and before IMR7 has been
set by any instruction.
10.4.3 Interrupt Request (IRQ) Register
Initialization
IRQ (Figure 10-9) is a read/write register that
stores the interrupt requests for both vectored
and polled interrupts. When an interrupt is made
on any of the six levels, the corresponding bit
position in the register is set to 1. Bits DO-OS
are assigned to interrupt requests IRQO-IRQ5'
respectively.
R251 IMR
Interrupt
Mask Register
(% FB; Read/Write)
1 ENABLES IROO
1 ENABLES IR01
1 ENABLES IR02
1 ENABLES IR03
1 ENABLES IR04
1 ENABLES IR05
1 ENABLES INTERRUPTS
Figure 10-8. Interrupt Mask Register
3047-095, 3047-064
Interrupts
IRQ is held in a Reset state until an EI instruc-
tion is executed. For polled processing, IRQ must
still be initialized by an EI instruction, but IMR
should first be cleared to 0 to individually
inhibit a 11 interrupt requests while interrupts
are globally enabled:
CLR IMR
EI
01
10.5 IRQ SOFTWARE INTERRUPT GENERATION
IRQ can be used to generate software interrupts by
specifying IRQ as the destination of any instruc-
tion referencing the register file. These Soft-
ware Interrupts (SWI) are controlled in the same
manner as hardware-generated requests, i.e., the
IPR and the IMR control the priority and enabling
of each SWI level.
To generate an SWI, the desired request bit in the
IRQ is set as follows:
OR IRQ,ItIRQLVL
where the immediate data, IRQLVL, has a 1 in the
bit position corresponding to the level of the SWI
desired. For example, if an SWI on level 5 is
desired, IRQLVL would have a 1 in the bit 5 posi-
tion:
OR IRQ,#%200100000
where the immediate data is preceded by %2 to
indicate a binary constant. With this instruc-
tion, if the interrupt system is globally enabled,
level 5 is enabled, and there are no higher prior-
ity pending requests, control is transferred to
the service routine pointed to by the level 5
vector.
R250 IRQ
Interrupt
Request Register
(% FA; Read/Write)
~
I L'ROO
~IR01
IR02
IR03
~------------IR04
L----------------IR05
Figure 10-9. Interrupt Request Register
10-5

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English