ZiLOG Z8 Technical Manual

10.1 INTRODUCTION
The 'l8 microcomputer allows six different inter-
rupt levels from eight sources: the four Port 3
lines P30-P33 make up the external interrupt
sources while serial in, serial out, and the two
counter/timers make up the internal sources.
These interrupts can be masked and their prior-
ities set by using the Interrupt Mask and the
Interrupt Priority registers. All six interrupts
can be globally disabled by resetting the master
Interrupt Enable bit D7 in the Interrupt Mask reg-
ister with a Disable Interrupt (D1) instruction.
Interrupts are globally enabled by setting D7 with
an Enable Interrupt (EI) instruction.
There are three interrupt control registers: the
Interrupt Request register (IRQ), the Interrupt
Mask. register (IMR), and the Interrupt Priority
register (IPR). Figure 10-1 shows addresses and
identifiers for the interrupt control registers.
Figure 10-2 is a block diagram showing the
Interrupt Mask and Interrupt Priority logic.
The l8 family supports both vectored and polled
interrupt handling. Details on vectored and
polled interrupts can be found in Sections 10.6
and 10.7.
DEC HEX IDENTIFIERS
..------ ....
251 INTERRUPT MASK FB IMR
250
INTERRUPT REQUEST FA IRQ
249 INTERRUPT PRIORITY F9 IPR
Figure 10-1. Interrupt Control Registers
Chapter 10
Interrupts
10.2 INTERRUPT SOURCES
Table 10-1 presents the interrupt types, sources,
and vectors available in the l8 family of
processors.
10.2.1 External Interrupt Sources
External sources involve interrupts request lines
IRQO-IRQ3' IRQO' IRQ1' and IRQ2 are always gen-
erated by a negative edge signal on the corre-
sponding Port 3 pin (P3
Z
' P33'
P31 correspond to
IRQO' IRQ1, and 1RQZ' respectively). Figure 10-3
is a block diagram for interrupt sources IRQO'
IRQ1' and IRQ2'
When the Port 3 pin (P3
1
,
P3
2
,
or P33) goes low,
the first flip-flop is set. The next two flip-
flops synchronize the request to the internal
clock and delay it by four external clock
periods. The output of the last flip-flop (IRQO'
IRQ1' or IRQ3) goes to the corresponding Interrupt
Request register.
INTERRUPT
REQUEST
GLOBAL
INTERRUPT
ENABLE
IRQo-IRQS
VECTOR SELECT
Figure 10-2. Interrupt Block Diagraa
6
3047-036.3047-037 10-1

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English