ZiLOG Z8 Technical Manual

'-
• When registers RO and R1 (Ports 0 and 1) are
defined as address outputs, they will return
1s in each address bit location when read.
• Writing to bits which are defined as address
output, timer output, serial output, or hand-
shake
output will have no effect.
• Instruction DJNZ uses a general register as a
counter. Only registers R4-R127 can be used
with this instruction.
3.3 CPU CONTROL AND PERIPHERAL REGISTERS
The ZS control registers govern the operation of
the CPU. Any instruction that references the
register file can access these control registers.
Available control registers are:
•
Interrupt Priority register (IPR)
•
Interrupt Mask register
(IMR)
•
Interrupt Request register
(IRQ)
•
Program Control flags (FLAGS)
•
Register Pointer
(RP)
•
Stack Pointer
high-byte
(SPH)
•
Stack Pointer - low-byte
(SPL)
The ZS uses a 16-bit Program Counter (PC) to
determine the sequence of current program instruc-
tions. The PC is not an addressable register.
Peripheral registers are used to transfer data,
configure the operating mode, and control the
operat ion of the on-chip peripherals. Any
instruction that references the register file can
access peripheral registers. The peripheral regis-
ters are:
•
Serial
I/O
(510)
•
Timer Mode
(TMR)
•
Timer/Counter 0
(TO)
•
TO Prescaler
(PREO)
•
Timer/Counter
1
(T1)
•
T1 Prescaler
(PRE1)
•
Port 0-1 Mode
(P01M)
•
Port 2 Mode
(P2M)
•
Port 3 Mode
(P3H)
In addition,
the
four port
considered to be peripheral
regist ers (PO-P3) are
registers.
The functions and applications of control and
peripheral registers are described in subsequent
sections of this manual.
Address Spaces
3.4 CPU PROGRAM MEMORY
The ZS can access 64K bytes of program memory with
the 16-bit Program Counter. In the ZS601, the
lower 2K bytes of the program memory address space
are internal ROM, while in the ZS611 the lower 4K
bytes are internal ROM. In the ZS6S2 the lower 2K
bytes are not accessible.
To access program memory outside the on-board ROM
space, Port 0 and Port 1 can be configured as a
memory interface. For example, Port 1 as a multi-
plexed Address/Data port (ADO-AD7) provides
Address lines AO-A7 and Data lines DO-D7. Port 0
can be configured for an additional four or eight
address lines (A
S
-A
11
or A
S
-A15). This memory
interface is supported by the control lines AS
(Address Strobe), 55 (Data Strobe) and R/W
(Read/Write).
In the ROMless Z8681 version, Port 1 is automati-
cally a multiplexed Address/Data port. Port 0
must be configured for additional address lines as
needed.
The first 12 bytes of program memory are reserved
for the interrupt vectors. Addresses 0-11 contain
six 16-bit vectors that correspond to the six
available interrupts. Figure 3-5 illustrates the
order of 16-bit data stored in program memory.
6
Location of
first byte of
instruction
executed
after reset
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
5535
EXTERNAL
ROM OR RAM
2048
2047
ON·CHIP
ROM
"'--
~------------
12
11 IR05
10
IR05
9
IR04
8
IR04
7
IR03
6 IR03
5~
IR02
4~
IR02
3
IR01
2 IR01
IROO
0
IROO
Figure 3-5a. Z8601 Program Memory Map
2037·004 3-3

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English