ZiLOG Z8 Technical Manual

5.6 Z8
Instruction
Descriptions
and Formats
"'--
ADC
dst,src
Instruction ro~t:
OPC
OPC
OPC
Operation:
flags~
EXBq)le:
Note:
ADC
Add With Carry
OPe Address Mode
Cycles
(Hex)
dot arc
I
I
dst src
I
6
12
r
r
13
r
Ir
I
I
src
I
I
dst
10 14
R
R
15 R
IR
I
I
dst
I I
src
10
16
R
1M
17 IR
1M
dst <-- dst + src + c
The source operand, along with the setting of the C flag, is added to the destination
operand and the sum is stored in the destination. The contents of the source are not
affected. Two's complement addition is performed. In multiple precision arithmetic,
this instruction permits the carry from the addition of low-order operands to be
carried into the addition of high-order operands.
C: Set if there is a carry from the most-significant bit of the result; cleared
otherwise
Z: Set if the result is zero; cleared otherwise
5: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign
and the result is of the opposite sign; cleared otherwise
0: Always cleared
H: Set if there is a carry from the most-significant bit of the low-order four bits
of the result; cleared otherwise
If the register named SUM contains ~16, the C flag is set to 1, working register 10
contains %20 (32 decimal), and register 32 contains ~10, the statement
AOC SUM,BR10
leaves the value ~27 in Register SUM.
cleared.
The C, Z, S, V, 0, and H flags are all
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E src/dst
5-7

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English