ZiLOG Z8 Technical Manual

ADD
Add
ADO dst,src
Instruction For.at:
ope
ope
ope
Operation:
Flags:
Example:
Note:
5-8
OPC Address Mode
Cycles
(Hex)
dst arc
I
I
dst src
I
6
02 r
r
03
r
Ir
I
I
src
I I
dst
10 04
R
R
05 R IR
I
I
dst
I I
src
10 06 R
1M
07 IR 1M
dst <-- dst + src
The source operand is added to the destination operand and the sum is stored in the
destination. The contents of the source are not affected. Two's complement addition
is performed.
C: Set if there was a carry from the most-signi ficant bit of the result; cleared
otherwise
Z: Set if the result is zero; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign
and the result is of the opposite sign; cleared otherwise
S: Set if the result is negative; cleared otherwise
H: Set if a carry from the low-order nibble occurs
0: Always reset to 0
If the register named SUM contains %44 and the register named AUGEND contains %11,
the statement
ADD SUM,AUGEND
leaves the value %55 in register SUM and leaves all flags cleared.
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
src/dst

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English