ZiLOG Z8 Technical Manual

AN>
dst,src
Instruction For.at:
OPC
OPC
OPC
Operation:
Flags:
'.
Example:
Note:
AND
Logical
OPC
Address Mode
Cycles
(Hex)
dst
src
I
I
dst src
I
6 52
r r
53
r
IR
I I
src
I I
dst
10 54
R R
55
R IR
I I
dst
I
I
src
10
56
R
1M
57 IR 1M
dst <-- dst AND src
The source operand is logically ANDed with the destination operand. The result is
stored in the destination. The AND operation results in a 1 bit being stored
whenever the corresponding bits in the two operands are both 1s; otherwise a 0 bit is
stored. The contents of the source bit are not affected.
C: Unaffected
Z: Set if the result is zero; cleared otherwise
V: Always reset to 0
S: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
0: Unaffected
If the source operand is the immediate value %78 (01111011) and the register named
TARGET contains %C3 (11000011), the statement
AND TARGET, 11%78
leaves the value %43 (01000011) in register TARGET.
cleared.
The Z, V, and S flags are
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
src/dst
5-9

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English