ZiLOG Z8 Technical Manual

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The lower nibble of Port 0 can be defined as
address lines A
8
-A
11
, by setting D1 to 1. Simi-
larly, setting D7 to 1 defines the upper nibble of
Port 0 as address lines A12-A15.
Whenever
Port 0 is configured to output address
lines A
12
-A
15
, A
8
-A
11
must also by selected as
address lines.
7.3.3 Read/Write Operations
If Port 0 is configured for address lines A7-A15'
it can no longer be used as a register; however,
if only the lower nibble of Port 0 is defined as
address lines A8-A11' the upper nibble is still
addressable as an I/O register. When only the
lower nibble is defined as address outputs, read-
ing Port 0 returns XF, where X equals the data in
bits D
4
-D7. Writing to Port 0 transfers data to
the I/O nibble only.
The instruction used to change the mode of Port 0
should not be immediately followed by an instruc-
tion that performs a stack operation, because this
will cause indeterminate program flow. In addi-
tion, after setting the mode of Port 0 for memory,
the next three bytes must be fetched without
changing the value of the upper byte of the Pro-
gram Counter (PC).
7.4 EXTERNAL STACKS
The l8681/82 architecture supports stack opera-
tions in either the register file or data memory.
A stack's location is determined by bit D2 in the
Port 0-1 Mode register. For example, if D2 is set
to 0, the stack is in external data memory
(Figure 7-7).
The instruction used to change the stack selection
bit should not be immediately followed by the
instructions RET or IRET, because this will cause
indeterminate program flow.
7.5 DATA MEMORY
The two memory spaces, data and program, can be
addressed as a single memory space or as two
separate spaces of equal size; i.e. 64K bytes each
for the l8681 and 62K bytes each for the l8682.
If the memory spaces are separated, program memory
and data memory are logically selected by Data
Memory select output (DM). DM is made available
on Port 3, line 4 (P3
4
) by setting bits D4 and D3
in the Port 3 Mode register to 10 or 01 (Figure
7-8). OM is active Low during the execution of
the LDE, LDEI instructions. DM is also active Low
during the execution of CALL, POP, PUSH, RET and
IRET instructions if the stack resides in memory.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
P0
4
-P0
7
MODE ~
OUTPUT = 00 ~
INPUT = 01
A
12
-A
15
= 1X
-r PO
O
-P0
3
MODE
L 00 = OUTPUT
01 = INPUT
1X = As-A11
L..- _____ P1
o
-P1
7
MODE
10 = ADo-AD7
Figure 7-6. Z8682 Port 0 Memory Operation
7-4 3047-001

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English