ZiLOG Z8 Technical Manual

Interrupts
10.4.1 Interrupt Priority Register (IPR)
Initialization
IPR (Figure 10-7) is a write-only register that
sets priorities for the six levels of vectored
interrupts in order to resolve simultaneous
interrupt requests. (There are 48 sequence
possibilities for interrupts.) The six interrupt
levels IRQO-IRQ5 are divided into three groups of
two interrupt requests each. One group contains
IRQ3 (SI!P3
0
) and IRQ5 (T 1)' another group
contains IRQO (P3
2
) and IRQ2 (P3
1
), and the third
group contains IRQ1 (P3
3
)
and IRQ4 (SO/TO).
Priorities can be set both within and between
groups as shown in Table 10-2. Bits 0
1
,
02' and
05 define the priority of the individual members
within the three groups. Bits DO' 03' and 04 are
encoded to define six priority orders between the
three groups. Bits 06 and 0
7
are not used.
R2491PR
Interrupt
Priority Register
(% F9; Write Only)
Group
C
B
A
10-4
IRQ3, IRQ5 PRIORITY (GROUP Aj ~
o = IRCS > IRC3
1 = IRC3 > IRCS
IRCO, IRC2 PRIORITY (GROUP B)
o = IRC2 > IRCO ------- ..
1 = IRCO > IRC2
IRC1, IRC4 PRIORITY
(GROUP C)
o = IRC1 > IRC4 --------..1
1 = IRC4 > IRC1
INTERRUPT GROUP PRIORITY
RESERVED = 000
C > A > B 001
A> B > C 010
A> C > B 011
B > C > A 100
C> B > A 101
B>A>C 110
RESERVED 111
Figure 10-7. Interrupt Priority Register
Table 10-2. Interrupt Priority
Bit Priority
Highest
Bit Pattern
Lowest
Group
Priority
Highest --> Lowest
°1=0
IRQ1 IRQ4
°4
1 IRQ
4
IRQ1
0
°2=0
IRQ2 IRQO
0
1
IRQO IRQZ
0
0
°s=O
IRQS IRQ3
1 IRQ
3
IRQS
O
2
DO
0 0
0
0
1
0 0
0 1
0
NOT USED
CAB
ABC
A C B
B C A
C B A
B A C
NOT USED
3047-094

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English