ZiLOG Z8 Technical Manual

External Interface (Z8601,Z8611)
6.8 EXTENDED BUS TIMING
The Z8601 and Z8611 can accommodate slow memory
access times by automatically inserting an addi-
tional state time (Tx) into the bus cycle. This
stretches the DS timing by two clock periods,
though internal memory access time is not
affected. Timing is extended by setting bit DS in
the Port 0-1 Mode register to 1 (Figure 6-8).
Figures 6-9a and 6-9b illustrate extended memory
Read and Write cycles.
R248 P01M
Port 0-1 Mode Register
(%
F8; Write Only)
EXTERNAL MEMORY TlMINGJ
NORMAL = 0
*EXTENDED = 1
"ALWAYS EXTENDED
TIMING AFTER RESET EXCEPT Z8682
Figure 6-8. Extended Bus Timing
I------------
r
-, MACHINE CYCLE-
r
-
x
--------
r
-
3
---t, I
r
1
CLOCK
PO
As-A15 ~
=x
-------"--
P1
=x
Ao-A7
)
.... ----------------c( 0
0
-0
7
IN >--C
AS
\-----.I
OS
\
~---------------------_I
R/W
~
OM
=x
_______ ~x=
I
~---------------------REAOCYCLE---------------------~II
Figure 6-9a. Extended External Instruction Fetch, or Memory Read Cycle
6-6 3047-005,3047-047

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English