ZiLOG Z8 Technical Manual

R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
L
STACK SELECTION
o = EXTERNAL
1
= INTERNAL
figure 1-1. External Stack Operation
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
o 0 P33 = INPUT
o 1 P33 = INPUT
1 0 P33 = INPUT
1 1 P33 = DAVlIRDY1
P34 = OUTPUT
P34 = OM
P34 = OM
P34 = RDYlIDAV1
figure 1-8. Port 3 Data Memory Operation
1.6 BUS OPERATION
Typical data transfers between the Z8681/82 and
memory are illustrated in Figure 6-6. Machine
cyc
les can vary from six to twelve c lock periods
depending on the operation being performed. The
notations used to describe the basic timing
periods of the Z8681/82 are: machine cycles (Mn),
timing
states (Tn), and clock periods. All timing
references are made with respect to the output
signals AS and 55. The clock is shown for clarity
only and does not have a specific timing relation-
ship with other signals.
3047-002,3047-003,3047-005
External Interface (Z8681,Z8682)
1.6.1 Address Strobe (AS)
All transactions start with AS driven Low and then
raised High by the Z8681/82. The rising edge of
AS indicates that R/W, OM (if used), and the
addresses output from Ports 0 and 1 are valid.
The addresses output via Port 1 remain valid only
during MnT1 and typically need to be latched using
AS, whereas Port 0 address outputs remain stable
throughout the machine cycle.
1.6.2 Data Strobe (OS)
The Z8681/82 uses 55 to time the actual data
transjer. For Write operations (R/i = Low), a Low
on 55 indicates that valid data is on the Port 1
ADO-AD7 lines. For Read operations (R/W = High),
the Address/Data bus is placed in a high-impedance
state before driving 55 Low so that the addressed
device can put its data on the bus. The Z8681/82
samples this data prior to raising 55 High.
1.1 EXTENDED BUS TIMING
The Z8681/82 accommodates slow memory access times
by automatically inserting an additional software-
controlled state time (Tx). This stretches the 55
timing by two clock periods. Timing is extended
by setting bit D5 in the Port 0-1 Mode register to
1 (Figure 7-9).
Refer to Section 6.7 for other figures pertaining
to extended bus timing.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
EXTERNAL MEMORY TIMINGJ
NORMAL = 0
"EXTENDED
= 1
·ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682
Figure 1-9. Extended Bus Timing
7-5

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English