ZiLOG Z8 Technical Manual

2
3 4 5
ROY
(INPUT TO Z8)
DAV
(OUTPUT
FROM Z8)
DATA ON PORT
VALID DATA
(OUTPUT FROM Z8)
State 1. RDY input is High indicating that the I/O device is ready to accept data.
State 2. The Z8 writes to the port register to initiate a data transfer. Writing the port outputs
new data and forces r5AV Low if and only if RDY is High.
State 3. The 1/0 device forces RDY Low after latching the data. RDY Low causes an inter·
rupt request to be generated. The Z8 can write new data in response to RDY going
Low; however, the data is not output until State 5.
State 4. The DAV output from the Z8 is driven High in response to RDY going Low.
State 5. After DAV goes High, the 1/0 device is free to raise RDY High thus returning the in·
terface to its initial state.
Figure 9-16. zn Output Handshake
l/U Ports
Figures 9-17 and 9-18 illustrate the strobed
handshake connections.
9.7 I/O PORT RESET CONDITIONS
A
P2o-P27
K
'I
Z8
I/O
DEVICE
DAV
P31
Figure 9-17. Input Strobed Handshake
using Port 2
~
P
2
o-
P2
7
)
r
Z8
1/0
DAV
DEVICE
P3s
ROY 1
P31
Figure 9-1B. Output Strobed Handshake
using Port 2
3047·093, 3047·08t, 3047·063
After a hardware reset, mode registers P01M, P2M,
and P3M are set as shown in Figures 9-19 - 9-22.
Ports 0, 1 and 2 are configured for input opera-
tion on all bits, except Port 1 in the Z8681 and
Ports 0 and 1 in the Z8682 as shown.
The pull-ups of Port 2 are set for open-drain. If
active pull-ups are desired for Port 3 outputs,
remember to configure them using P3M (Figure
9-22).
All special I/O functions of Port 3 are inactive,
with P3
0
-P3
3
set as inputs and P3
4
-P3
7
set as
outputs (Figure 9-23).
9-9

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English