ZiLOG Z8 Technical Manual

Once Port 1 is configured as an Address/Data port,
it can no longer be used as a register. Attempt-
ing
to read Port 1 returns FF; writing has no
effect. Similarly, if Port 0 is configured for
address lines A
S
-A
15
, it can no longer be used as
a register. However, if only the lower nibble is
defined as address lines AS-A11' the upper nibble
is still addressable as an I/O register. Reading
Port 0 with only the lower nibble defined as
address outputs returns XF, where X equals the
data in bits 04-D7. Writing to Port 0 transfers
data to the I/O nibble only.
An instruction to change the modes of Ports 0 or 1
should not be immediately followed
by an instruc-
tion that performs a stack operation, because this
may cause indeterminate program flow. In addi-
tion, after setting the modes of Ports 0 and 1 for
external memory, the next three bytes must be
fetched from internal program memory.
6.4 EXTERNAL STACKS
ZS architectUre supports stack operations in
either the register file or data memory. A
stack I s location is determined by bit 02 in the
Port 0-1 Mode register. For example, if D2 is set
to 1, the stack is in internal data memory
(Figure 6-4).
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
L
STACK SELECTION
o = EXTERNAL
1
= INTERNAL
Figure 6-4. Ports 0 and 1 Stack Selection
The instruction used to change the stack selection
bit should not be immediately followed by the
instructions RET or IRET, because this will cause
indeterminate program flow.
3047-002. 3047-003
External Interface (ZS601,ZS611)
6.5 DATA I£tI1RY
The two external memory spaces, data and program,
can be addressed
as a single memory space or as
two separate spaces of equal size; i.e., 62K bytes
each for theZS601 and 60K bytes each for the
ZS611. If the memory spaces are separated,
program memor.y and data memory are logically
se lected by the Oata Memory select output (DM).
DM is available on Port 3, line 4 (P3
4
) by setting
bits 04 and D3 in the Port 3 Mode register to 10
or 01 (Figure 6-5). 'D'M is active Low during the
execution of the LDE, LDEI instructions. OM is
also active dur ing the execution a f CALL, POP,
PUSH, RET and IRET instructions if the stack
resides in external memory.
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
o 0 P33 = INPUT
o 1 P33 = INPUT
1 0 P33 = INPUT
1 1 P33 = OAV1/ROY1
P34 = OUTPUT
P34 = D"M
P34 = OM
P34 = ROY1/DAV1
Figure 6-5. Data Memory Operation
6.6 BUS OPERATION
The timing for typical data transfers between the
ZS and external memory is illustrated in Figure
6-6. Machine cycles can vary from six to twelve
clock periods depending on the operation being
performed. The notations used to describe the
basic timing periods of the ZS are: machine cycles
(Mn), timing states (Tn), and clock periods. All
timing references are made with respect to the
output signals AS and DS. The clock is shown for
clarity only and does not have a specific timing
relationship with other signals.
6-3

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English