ZiLOG Z8 Technical Manual

External Interface (ZS601,ZS611)
POO-P07, P1
0
-
P1
7' P2
0
-
P2
7, P30-P37. I/O port
lines (inputs/outputs, TTL-compatible, pins
12-40). These 32 I/O lines are divided into four
S-bit I/O ports that can be configured under pro-
gram control for I/O or external memory inter-
face. Individual lines of a port are denoted by
the second digit of the port number. For example,
P3
0
refers to bit 0 of Port 3. Ports 0 and 1 can
be
placed in a high-impedance state along with AS,
DS, and R/W.
RESET. Reset (input, active Low, pin 6). RESET
initializes the ZS. When RESET is deaet. i vated,
program execution begins from internal program
location %C. If held Low, RESET acts as a regis-
ter file protect during power-down and power-up
sequences. RESEr also enables the ZS Test mode.
X TAL 1, XTAL2. Crystal 1, Crystal 2 (oscillator
I input and output, pins 3 and 2). These pins con-
nect a parallel-resonant crystal (12 MHz maximum)
or an external source (12 MHz maximum) to the
on-board clock oscillator and buffer.
6.3 CONfIGURING fOR EXTERNAL MEMORY
Before interfacing with external memory, the user
must configure Ports 0 and 1 appropriately. The
minimum bus configuration uses Port 1 as a multi-
plexed Address/Data port (AD
O
-AD
7
) , allowing
access to 256 bytes of external memory. In this
configuration, the eight lower order address bits
(A
O
-A
7
) are multiplexed with the data (D
O
-D7).
Port 0 can be programmed to provide four addi-
tional address lines (AS-A11)' which increases the
externally addressable program memory to 4K
bytes. Port 0 can also be programmed to provide
eight additional address lines (A
S
-A15)' which
increases the externally addressable memory to 62K
bytes for the ZS601 or 60K bytes for the ZS611.
Refer to Chapter 3, Figures 3-5 and 3-6, for
external memory maps.
Ports 0 and 1 are configured for external memory
operation by writing the appropriate bits in the
Port 0-1 Mode register (Figure 6-3).
F or example, Port 1 can be defined as a mult i-
plexed Address/Data port (ADO-AD7) by setting D4
to 1 and D3 to O. The lower nibble of Port 0 can
be defined as address lines A
S
-A11' by setting D1
to 1. Similarly, setting D7 to 1 defines the upper
nibble of Port 0 as address lines A
12
-A15. When-
ever Port 0 is configured to output address lines
A12-A15' AS-A11 must also be selected as address
lines.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
P0
4
-P0
7
MODE
I'
OUTPUT = 00 ~
INPUT = 01
A
12
-A
15
= 1X
--r- PO
O
-P0
3
MODE
L 00 = OUTPUT
01 = INPUT
1X = As-All
P1
0
-P1
7
MODE
00
= BYTE OUTPUT
01 = BYTE INPUT
10
= ADo-AD7
11 = HIGH·IMPEDANCE ADo-AD1,
AS, Os, RtW, As-A11, A12-A15
figure 6-3. Ports 0 and 1 External Memory Operation
6-2 3047-001

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English