ZiLOG Z8 Technical Manual

10.2.2 Internal Interrupt Sources
Internal
IRQ3-IRQ5·
sources involve interrupt requests
If Serial In is enabled, IRQ3 gen-
erates an interrupt request whenever the receiver
assembles a complete byte. Interrupt level IRQ4
has two mutually exclusive sources, Counter/Timer
o (TO) and the Serial Out transmitter. If Serial
Out is enabled, an interrupt request is generated
when the transmit buffer is empty. If TO is
enabled, an interrupt request is generated at TO
end-of-count. IRQ5 generates an interrupt request
at Counter/Timer 1's (T1) end-of-count.
For more details on the internal interrupt
sources, refer to the chapters describing serial
I/O and the counter/timers.
10.J INTERRUPT REQUEST (IRQ) REGISTER lOGIC AND
TIMING
Figure 10-5 shows the logic diagram for the
Interrupt Request register. The leading edge of
the request will set the first flip-flop, which
will remain set until interrupt requests are
sampled.
IROo-IROs
Q
SAMPLE
CLOCK
Interrupts
Requests are sampled internally during the last
clock cycle before an opcode fetch (Figure 10-6).
External requests are sampled two internal clocks
earlier, due to the synchronizing flip-flops shown
in Figures 10-3 and 10-4.
At sample time the request is transferred to the
second flip-flop in Figure 10-5, which drives the
interrupt mask and priority logic. When an
interrupt cycle occurs, this flip-flop will be
reset only for the highest priority level that is
enabled.
The user has direct access to the second flip-flop
by reading and writing the IRQ register. IRQ is
read by specifying it as the source register of an
instruction and written by specifying it as the
destination register.
10.4 INTERRUPT INITIALIZATION
After reset, all interrupts are disabled and must
be initialized before vectored or polled interrupt
processing can begin. The Interrupt Priority reg-
ister (IPR), Interrupt Mask register (IMR) and
Interrupt Request register (IRQ) must be initial-
ized, in that order, to start the interrupt
process. However, IPR need not be initialized for
polled processing.
S
R
Q
TO MASK
AND
PRIORITY
LOGIC
FROM PRIORITY
LOGIC
Figure 10-5. IRQ Register logic
L..... ______ EXTERNAL INTERRUPT
REQUESTS
SAMPLED
Figure 10-6. Interrupt Request T:iJning
3047-040, 3047-041 10-3

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English