ZiLOG Z8

External Interface (Z8601,Z8611)
6.10 RESET CONDITIONS
After a hardware reset, Ports 0 and 1 are con-
figured as input ports, memory and stack are
internal, extended timing is set and OM is
inactive. Figure 6-13 shows the binary values
reset into P01M.
6-10
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
P0
4
-P0
7
MODE~
OUTPUT = 00 ~
INPUT = 01
A
12
-A
15
= 1X
EXTERNAL MEMORY TIMING
NORMAL
= 0
*EXTENDED = 1
I [ P08oP~, ~U~~~T
01 = INPUT
1X = As-All
STACK SELECTION
o = EXTERNAL
1
= INTERNAL
P1
o
-P1
7
MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD7
11 = HIGH·IMPEDANCE ADo-AD7,
AS, Os, RNi, As-All, A12-A15
"ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682
figure 6-13. Ports 0 and 1 Reset
3047·006