ZiLOG Z8 Technical Manual

Architectural Overview
2.3 REGISTER FILE
The Z8's register-oriented architecture centers
around an internal register file composed of 124
general-purpose registers, 16 CPU and peripheral
control registers, and 4 I/O port registers. All
registers are eight bits. Any general-purpose
register can be used as an accumulator, an address
pointer, or an index, data, or stack register.
2.3.1 Register Pointer
A Register Pointer logically divides the register
file into 9 working register groups of 16 regis-
ters each, which allows for fast context switching
and shorter instruction formats.
2.3.2 Instruction Set
The Z8 CPU has an instruction set designed for the
large register file. The instruction set provides
a full complement of 8-bit arithmetic and logical
operations. BCD operations are supported using a
decimal
adjustment 0 f binary values, and 16-bi t
quantities for addresses and counters can be
incremented and decremented. Bit manipUlation and
Rotate and Shift instructions complete the data
manipulation capabilities of the Z8 system. No
special I/O instructions are necessary since the
I/O is mapped into the register file.
2.3.3 Data Types
The Z8 CPU supports operations on bits, BCD
digits, bytes, and 2-byte words.
Bits in the register file can be tested, set,
cleared, and complemented. Bits within a byte are
numbered from 0 to 7 with bit 0 being the least
significant (right-most) bit (Figure 2~2).
Figure 2-2. Bits in Register
Manipulation of BCD digits packed two-to-a-byte is
accomplished by a Decimal Adjust instruction and a
Swap instruction. Decimal Adjust is used after a
binary addition or subtraction on BCD digits.
2-2
Logical, Shift, Rotate and Load instructions oper-
ate on bytes in the register file. Bytes in data
memory are only affected by Load instructions.
Sixteen-bit arithmetic instructions (Increment
Word and Decrement Word) operate on words in the
register file.
2.3.4 Addressing Hodes
The addressing modes of the Z8 CPU are:
• Register
• Indirect Register
• Immediate
• Direct Address
• Indexed (with a short 8-bit displacement)
• Program Counter Relative
Register, Indirect Register, and Immediate
addressing modes are available for Load, Ar ith-
metic, Logical, Shift, Rotate, and Stack instruc-
tions. Conditional Jumps use both Direct Address
and Program
Counter Relative, while Jump and Call
instructions use Direct Address and Indirect Reg-
ister addressing modes.
2.4 I/O OPERATIONS
The Z8 has 32 pins dedicated to input and output.
These lines are grouped into four ports of eight
lines each. Ports can be programmed as input,
output, or bidirectional. Under software control,
the ports provide timing, status signals, address
outputs, and serial or parallel I/O with or with-
out handshake. Multiprocessor system configura-
tions are also supported.
2.4.1 Timers
To unburden the program from real-time problems
such
as serial data communications and counting/
timing, the Z8 contains an on-chip universal asyn-
chronous receiver/transmitter (UART) and two coun-
ter/timers with a large number of user-selectable
modes. One on-chip timer provides the bit rate
input to the UART during communications.
2.4.2 Interrupts
I/O operations can be interrupt-driven or polled.
The ZB supports six vectored interrupts that can
be masked and
prioritized.
3047-072

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English